Abstract: The disclosure describes improved apparatus and method for implementing the test of various computer functional units interconnected by a common bus. At the beginning of the method, each functional unit is subjected to an enforced condition which disconnects it from the bus. Then, one of the units is subjected to an enforced condition which connects it to the bus and is tested under microprogram control. After the one unit has been tested, another unit is connected to the bus and is tested. In this manner the functional units after first being disconnected from the common bus are reconnected and tested one at a time and those units which have no error detected therein are maintained connected.
Abstract: A control arrangement for a belt printer having characters arranged in successive series on an endless belt and passed continuously in front of a print support and hammers adapted to be actuated by a control device. A recording store is connected to a calculating unit and records information relating to each character to be printed along a line on the print support. A scan register contains information relating to the coincidences between the characters and the striking members at any given time. Information corresponding to the condition when a predetermined character is to be struck by a given hammer in the course of a given scan, is stored in a storage member along with information indicative of whether or not the predetermined character is repeated in the series of characters.
Abstract: A support for integrated circuit chips to be mounted on an interconnecting base provided with conductive areas. The support consists of a flexible strip made of an inextensible insulating material having equidistant openings towards the center of each of which extend overhanging interface conductors electrically independent of each other. The free inner ends of the conductors in each opening correspond to that of the contact areas on a chip placed at the center of the opening, and each of the conductors has at a point along its overhanging portion, a contact region which is intended to be soldered to a corresponding conductive area on the said interconnecting base.
Abstract: An arrangement for sharing file information among plural processes in a multiprogrammed computing system. Source program file declarations are compiled into file control structures which are placed in skeletal segments, the segments forming units of potential sharing between active processes. Those segments which contain file control structures are placed in either the address space of (1) all processes, (2) related processes, or (3) a single process, depending upon the declared sharing level of the file. Job control language (JCL) commmands are expanded into JCL file control structures and merged with the source language structures to form a file request control structure. This request may be compared against a catalog of existing external files, a check being made to insure that the account on whose behalf a computing job is requesting file assignment is authorized to obtain the requested access to the file.
Abstract: A matching network for distributing high frequency bi-directional signals transmitted along a coaxial transmission line includes a transformer and an active filter having a second order transfer function for coupling a transmitter or a receiver to the transmission line. A comparator comprising trigger-connected differential amplifiers converts the output of the filter to bi-directional signals.
Abstract: The disclosure describes apparatus for handling detected errors in a data processing system. First means define and locate the detected errors and second means allow the attempted reexecution of the instruction being executed when the error is detected.
Abstract: The disclosure describes a data processing system including a program memory for storing a first instruction at a first address and a second instruction at a second address. The system includes a look-ahead feature in which the second instruction is stored in a buffer register while the first instruction is being stored in an execution register and is simultaneously being executed. A gate circuit controls the transmission of data between the buffer register and the execution register. If a third instruction having a third address is read into the program memory while the first instruction is being executed, the second and third addresses are compared. If the second and third addresses are identical, the gate circuit is inhibited and the second instruction is prevented from being transmitted to the execution register. Instead, the third instruction or a portion thereof, is transmitted to the buffer and execution registers, so that the third instruction is executed in place of the second instruction.
Abstract: A method of fabricating a carrier support for integrated circuit chips to be mounted subsequently on a substrate. A flexible strip of an inextensible insulating material is provided with equidistant openings in the center of each of which a chip is to be mounted. One of the faces of this strip is covered with a conductive film, the said film is cut away to form in each opening interface conductors which overhang towards the center of the opening. Before the conductive film is cut away, the film is coated with a layer of photosensitive lacquer which is partly removed to enable the film to be laid bare in regions which, in each opening, form part of an open-centered zone which surrounds that portion of the film in which the free inner ends of the interface conductors associated with this opening are to be produced.
Abstract: The disclosure describes a data processing system including a program memory for storing a first instruction at a first address and a second instruction at a second address. The system includes a look-ahead feature in which the second instruction is stored in a buffer register while the first instruction is being stored in an execution register and is simultaneously being executed. A gate circuit controls the transmission of data between the buffer register and the execution register. If a third instruction having a third address is read into the program memory while the first instruction is being executed, the second and third addresses are compared. If the second and third addresses are identical, the gate circuit is inhibited and the second instruction is prevented from being transmitted to the execution register. Instead, the third instruction, or a portion thereof, is transmitted to the buffer and execution registers, so that the third instruction is executed in place of the second instruction.
Abstract: Power supplies having power input excitation terminals and power output terminals are tested under differing load and excitation conditions. Excitation sources having differing parameters are selectively connected to the input terminals. A variable impedance load is connected to the output terminals. Voltage measuring apparatus is selectively connected to be responsive to the voltage derived from the selective connecting means and the voltage across the load and is selectively connected to a readout means. A dynamic signal source derives control signals for respectively controlling the parameters of the excitation sources, the impedance of the load, and the connections of the readout means and the measuring apparatus.
Abstract: An interface connects a data-processing unit to a group of m working stations, each including items of data emitting and receiving apparatus. The unit and each of the items of apparatus transmit and receive binary data in parallel characters in response to control signals generated by the unit. The characters are coupled between the interface and stations as serial bits via a separate channel that extends to each station. Each channel includes separate lines for sending the characters in opposite directions. At the interface, there are provided m transmitter/receiver circuits, one of which is associated with each of the m stations. There is a transmitter/receiver circuit associated with each item of apparatus at each of the stations. Each transmitter/receiver circuit includes a parallel to serial converter for each parallel input character supplied to it and a serial to parallel converter for each series character applied to it.
Abstract: An apparatus for positionally controlling the movable head assembly of a magnetic disc memory unit. In a first state, the head assembly is accelerated under substantially free conditions. In a second or deceleration state, the assembly speed is compared with and regulated by a series of theoretical speeds set in accordance with the actual speed attained by the movable head assembly during the first state.
Abstract: In printing data on paper sheets which are connected along lines of perforation, the paper advance relative to the printer is controlled to assure that the proper kind of data is printed in the appropriate area or areas of the sheet or sheets to which such kind of data has been assigned. Different levels of the sheet corresponding to these areas are identified by the number of spaces between such levels and the upper edge of the sheet and a control system is employed which monitors the position of the printing line with respect to the upper edge of the sheet and which controls the paper advance in accord with the levels of the areas.
Abstract: The disclosure describes improved apparatus for setting the states of storage elements in a data-processing system and for responding to the data read out of the storage elements. The apparatus includes a first error detector which enables an initial setting circuit to initially set a first storage element to a predetermined condition in response to an error. The initial setting circuit also disconnects the outputs of a second storage element while that element is receiving reference data and reconnects the outputs of the second storage element after the data has been written into that element. A second error detector monitors the outputs of the first and second storage elements as test signals are conducted to the storage elements.
Abstract: The disclosure describes apparatus for checking the operation of control circuits of the type used to actuate the hammers of a printer. A first gating matrix is addressed by a selector so that the control circuits are operated in groups during a plurality of sub-cycles of operation. Detectors which generate an error signal in response to the erroneous operation of each control circuit are connected to the gates of a second gating matrix arranged in the same manner as the first gating matrix. The selector also addresses the second gating matrix so that the detectors which generate error signals can be identified in an error register connected to the second gating matrix.
Abstract: This disclosure relates to a construction in a printer of the type utilizing an endless character-bearing band which is carried in a cartridge and which is mounted in the printer on two pulleys in a tensioned state, the construction including means for changing the spacing of the two pulleys only after a cartridge has been placed within the printer with the means being in the form of a key which rotates a cam and which key has associated therewith means for moving a protective member relative to the band when the key is in an operative position. The construction further includes locking means for preventing the insertion of the key into an operative position until such time as a cartridge is in position and the cover of the printer has been closed.
Abstract: An electromagnetic striker apparatus. The apparatus includes a core member, a coil associated with the core member and an armature member. The apparatus also includes means for guiding the armature member in movement relative to the core member. In response to actuation of the coil, the armature moves from a rest position to a strike position, whereby a character key is driven against a print support. Under the influence of the guiding means, the armature moves substantially parallel to the magnetic flux lines within the armature.
Abstract: An apparatus for accurately positioning a flexible strip, having lateral perforations, with respect to an image. The apparatus includes two supports, a stud member attached to the movable support and an intercepting arm attached to the fixed support. The stud member includes a working section for engagement of the lateral perforation and alignment of the strip and a biased sleeve for position maintenance of the strip. The intercepting arm stays action of the sleeve until alignment is substantially achieved.
Abstract: The disclosure describes an interface including data lines and address lines which address a memory. Control lines control the exchanges of data among the data lines, address lines, memory and data processing unit. A parity line provides a means of checking the accuracy of the information transmitted on the data or address lines.
Abstract: A data processing system having a common data bus to which access is gained by at least a control store, an arithmetic logic unit (ALU) and an emulator unit (EMU). The control store includes a microprogrammable switch for enabling either the EMU or the ALU to process instructions received on a common bus. Common opcode bits in the instruction are interpreted by either the ALU or the EMU and responded to thereby depending upon the state of a control register in the control store. The instructions are stored in a control store array in the control store coupled with the bus, and allows operation of either the ALU (native mode of operation) or the EMU (non-native mode of operation), dependent upon the microprogram's instruction in the control store thereby giving increased efficiency of operation of the system.