Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: An improved method for design and testing using a CAD system incorporating the automatic production of a bloc-structured hexahedral grid of a mathematically defined volume from a previously generated surface definition of the volume. A surface definition of an object is designed and stored in a CAD format, then numerically scanned to detect major geometric features. A structured, hexahedral grid is projected through the volume with a grid density and spacing conforming to the major geometric features of the surface definition. All grid elements which do not intersect the volume within surface definition are discarded, and the remaining surface nodes are projected onto the surface definition of the volume. Highly distorted elements resulting from the projection are minimized by iteratively smoothing nodes on the corners, edges, and surfaces of the surface definition by applying a relaxation algorithm.

Abstract: Method for enabling each of several processors in a multi-processing operating system to schedule processes it will execute without a supervisory scheduler. The processes are executed on the basis of priorities assigned to the processes. More than one processor can schedule processes simultaneously so long as each processor schedules processes having different priority levels from those being processed by another processor.

Abstract: An optical clock distribution method and apparatus is disclosed that minimizes clock skew in the distribution of clock signals to logic assemblies in a computer system. The logic assemblies convert the optical signals into equivalent electrical signals.

Abstract: A method for performing diagnostics on a CPU logic simulator executes certain portions of the diagnostics on a real-machine, and other portions in the software simulator. Those portions that must be executed in the simulator are executed on the simulator, while those portions that need not be executed on the simulator are preferably executed on the real-machine. The method coordinates the execution of the diagnostic functions between the real- machine and the simulator to achieve improved speed of diagnostic execution.

Abstract: A tightly coupled interprocessor communication system based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2.sup.N processors. A local control circuit is connected to each processor and a shared resource circuit is tightly coupled through the local control circuits to each processor. The shared resource circuit includes a shared semaphore register, a shared information register and a read and increment circuit which can be used to increment the contents of a shared information register as a single instruction. The local control circuit includes an issue control circuit used to determine when a transaction with the shared resource circuit is permitted, a circuit which generates a command to the shared resource circuit when the transaction is permitted and a real time clock.

Abstract: A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs.

Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters.

Abstract: A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.

Abstract: A digital optical serial communication system and encoding method comprises a transmitter responsive to an input of parallel information for parsing the information into 4-bit groups. The 4-bit groups are encoded into 5-bit codes having a 40/60 duty cycle and wherein no more than two consecutive bits are logical 1's or 0's on either end of the 5-bit code. The 5-bit codes are serially transmitted by an optical transmission medium for providing a conduit from the transmitter to a receiver. The receiver receives and decodes the serial information to 4-bit groups. The 4-bit groups are concatenated to form a parallel packet of information suitable for data processing. The encoding/decoding scheme has the advantages of (1) a worst case duty factor of 40/60%; (2) a maximum run of bits without transition equal to five; (3) an easily recaptured framing of packets due to a unique sync symbol; and (4) simple encoding and decoding of packets using combinational logic rather than lookup tables.

Abstract: A circuit monitors electronic devices which require continuous clocking for non-destructive operation. The circuit samples a repetitive signal, such as a clock, from a device of interest (DOI). If, for whatever reason, the clock signal becomes absent, the circuit responds by deactivating the DOI. If the clock revives or becomes intermittent the circuit will not reactivate the DOI. The circuit will reactivate the DOI only upon application of an explicit reset signal. The circuit is all digital and therefore technology independent, and provides for precise control of the deactivation response time.

Abstract: An apparatus for adjusting signal delay includes an input for receiving a signal to be delay adjusted. A delay circuit is connected to the input means for providing a plurality of selectable signal paths for various delay amounts for producing a delay adjusted signal therefrom. A delay selection circuit is connected to the delay circuit for selecting the signal path so as to select a delay amount and an output provides the delay adjusted signal to a load. Skew compensation is employed on the input and individually on each output to compensate for clock distribution network skew and intracircuit skews, respectively.

Abstract: The present invention includes a tooling apparatus designed to provide accurately aligned printed circuits on both major sides of a printed circuit board layer, especially advantageous for use in multi-layer PCB's. Also disclosed is the method manufacture of the apparatus and the methods of using the apparatus. The apparatus includes patterns formed on glass masks attached to frames incorporating alignment pins and slots. The patterns include registration marks for alignment during manufacture of the apparatus. During use, the apparatus allows accurate alignment of patterns on both sides of a PCB layer. Also disclosed is the apparatus with buttons used to pattern PCB layers having pre-drilled Z-axis holes.

Abstract: A completely shielded metallized connector block for use in multiple circuit modules of an electronic device. Electrical communication between the circuit boards is effected by an array of metallic pins which run through the blocks. The metallization on the nonconductive blocks can be held at ground or at a constant potential to increase the shielding between pins as well as maintaining voltage and ground planes at constant levels throughout the modules. The metallization is insulated from the pins and circuit boards by nonconductive bushings inserted in holes in the blocks. In one embodiment, the metallization consists of copper and solder plating and the blocks are constructed of liquid crystal polymer.

Abstract: A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.

Abstract: A method of providing fast and efficient kernel functions including those usually performed by kernel daemons and other kernel processes such as those which service interrupts. The method consists of using minimal-context processes that carry only the system-related information needed to do the work they are created to do. Compared to the full-context processes presently used to do kernel functions, minimal-context processes are created quickly and switch economically. If associated with a work queue, the minimal-context process performs a series of tasks within a single active session. If no queue is used, a minimal-context process can wake up and accomplish a single task rapidly. The method generally relates to kernel-based operating systems.

Abstract: The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.

Abstract: A digital optical serial communication system and encoding method comprises a transmitter responsive to an input of parallel information for parsing the information into 4-bit groups. The 4-bit groups are encoded into 5-bit codes having a 40/60 duty cycle and wherein no more than two consecutive bits are logical 1's or 0's on either end of the 5-bit code. The 5-bit codes are serially transmitted by an optical transmission medium for providing a conduit from the transmitter to a receiver. The receiver receives and decodes the serial information to 4-bit groups. The 4-bit groups are concatenated to form a parallel packet of information suitable for data processing. The encoding/decoding scheme has the advantages of (1) a worst case duty factor of 40/60%; (2) a maximum run of bits without transition equal to five; (3) an easily recaptured framing of packets due to a unique sync symbol; and (4) simple encoding and decoding of packets using combinational logic rather than lookup tables.