Patents Assigned to Cree, Inc.
  • Patent number: 10811573
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly packaged LEDs with light-altering materials are disclosed. A light-altering material is provided in particular configurations within an LED package to redirect light from an LED chip within the LED package and contribute to a desired emission pattern of the LED package. The light-altering material may also block light from the LED chip from escaping in a non-desirable direction, such as large or wide angle emissions. The light-altering material may be arranged on a lumiphoric material adjacent to the LED chip in various configurations. The LED package may include an encapsulant on the light-altering material and the lumiphoric material.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 20, 2020
    Assignee: Cree, Inc.
    Inventors: Kyle Damborsky, Derek Miller, Jack Vu, Peter Scott Andrews, Jasper Cabalu, Colin Blakely, Jesse Reiherzer
  • Patent number: 10811370
    Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 20, 2020
    Assignee: Cree, Inc.
    Inventors: Kyle Bothe, Dan Namishia, Fabian Radulescu, Scott Sheppard
  • Patent number: 10804452
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 13, 2020
    Assignee: Cree, Inc.
    Inventor: Michael Check
  • Patent number: 10804251
    Abstract: Devices, components and methods containing one or more light emitter devices, such as light emitting diodes (LEDs) or LED chips, are disclosed. In one aspect, a light emitter device component can include a metallic substrate with a mirrored surface, one or more light emitter devices mounted directly or indirectly on the mirrored surface, and one or more electrical components mounted on the top surface and electrically coupled to the one or more light emitter devices, wherein the one or more electrical components can be spaced from the mirrored metal substrate by one or more non-metallic layers. Components disclosed herein can result in improved thermal management and light output.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: October 13, 2020
    Assignee: Cree, Inc.
    Inventors: Erin R. F. Welch, Colin Kelly Blakely, Jesse Colin Reiherzer, Christopher P. Hussell
  • Patent number: 10797201
    Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: October 6, 2020
    Assignee: CREE, INC.
    Inventors: Kevin W. Haberern, Matthew Donofrio, Bennett Langsdorf, Thomas Place, Michael John Bergmann
  • Patent number: 10797204
    Abstract: Submount based light emitter components and related methods are disclosed. In some aspects, light emitter components include a reflective ceramic submount, at least one light emitter chip disposed over a first surface of the submount, a layer of optical conversion material disposed over portions of each of the at least one light emitter chip and the first surface of the submount, and a lens disposed over the layer of optical conversion material. The layer of optical conversion material and the lens define separate and discrete layers over the at least one light emitter chip and submount.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 6, 2020
    Assignee: Cree, Inc.
    Inventors: Jesse Colin Reiherzer, Erin R. F. Welch, Sung Chul Joo
  • Patent number: 10784825
    Abstract: An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 22, 2020
    Assignee: CREE, INC.
    Inventors: Haedong Jang, Timothy Canning, Bjoern Herrmann, Zulhazmi Mokhti, Frank Trang, Richard Wilson
  • Patent number: 10784338
    Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, Vipindas Pala, John Palmour
  • Patent number: 10770415
    Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: September 8, 2020
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 10767111
    Abstract: A method is disclosed for forming a blended phosphor composition. The method includes the steps of firing precursor compositions that include europium and nitrides of at least calcium, strontium and aluminum, in a refractory metal crucible and in the presence of a gas that precludes the formation of nitride compositions between the nitride starting materials and the refractory metal that forms the crucible. The resulting compositions can include phosphors that convert frequencies in the blue portion of the visible spectrum into frequencies in the red portion of the visible spectrum.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 8, 2020
    Assignee: CREE, INC.
    Inventors: Brian T. Collins, Christopher P. Hussell, David T. Emerson, Ronan P. Le Toquin
  • Patent number: 10763334
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 1, 2020
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 10756231
    Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include III nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 25, 2020
    Assignee: CREE, INC.
    Inventors: Thomas A. Kuhr, Robert David Schmidt, Daniel Carleton Driscoll, Brian T. Collins
  • Patent number: 10748996
    Abstract: A transistor device includes a semiconductor structure, a plurality of gate fingers extending on the semiconductor structure in a first direction, a plurality of gate interconnects that each have a first end and a second end extending on the semiconductor structure in the first direction, wherein each gate interconnect is connected to a respective gate finger by a plurality of first conductive vias, and a plurality of gate runners extending on the semiconductor structure in the first direction. At least one gate interconnect of the gate interconnects is connected to one of the gate runners by a second conductive via at an interior position of the at least one gate interconnect that is remote from the first end and the second end of the at least one gate interconnect.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 18, 2020
    Assignee: Cree, Inc.
    Inventors: Zulhazmi Mokhti, Frank Trang, Haedong Jang
  • Patent number: 10743404
    Abstract: A semiconductor device includes a metal base, a transistor die mounted on the metal base, a lid over the transistor die, and a multilayer printed circuit board electrically connected to the transistor die. The multilayer printed circuit board comprises a first portion positioned between the lid and the metal base, a second portion positioned outside of the lid, a plurality of embedded conductive layers, an embedded dielectric layer disposed between at least two of the plurality of embedded conductive layers, and at least one embedded reactive component formed from at least one of the embedded conductive layers.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 11, 2020
    Assignee: CREE, INC.
    Inventors: Qianli Mu, Cristian Gozzi, Asmita Dani
  • Patent number: 10741730
    Abstract: Stabilized luminescent nanoparticles for light emitting diode applications comprise perovskite nanocrystals encapsulated by an oxide coating, where the oxide coating includes ligand remnants comprising one or more elements selected from the group consisting of: nitrogen, carbon, phosphorus, and sulfur. A method of making the stabilized luminescent nanoparticles comprises dispersing perovskite nanocrystals and crosslinking ligands in a non-polar solvent to form a first mixture. Each of the crosslinking ligands comprises a head end and a tail end; the head ends attach to the perovskite nanocrystals and the tail ends remain unattached and available for crosslinking. An oxide precursor comprising crosslinking functional groups is added to the first mixture, and the crosslinking functional groups attach to the tail ends of the crosslinking ligands. Thus, an oxide coating is formed on the perovskite nanocrystals.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: August 11, 2020
    Assignee: CREE, INC.
    Inventors: Linjia Mu, Kenneth Lotito, Ryan Gresback
  • Patent number: 10734560
    Abstract: A device for an LED has a substrate and a circuit on the substrate configured to accept the LED. The circuit includes a first set of electrical traces terminating at a first set of solder pads for a first sized LED, a second set of electrical traces terminating at a second set of solder pads for a second sized LED different from the first sized LED, and peripheral electrical traces for electrically interconnecting electrical traces of the first set of electrical traces or between electrical traces of the second set of electrical traces. Connection components electrically interconnect the first set of electrical traces with each other or the electrical traces of the second set of electrical traces with each other, respectively, at corresponding solder pads. The device is configurable to provide a first voltage and a second voltage to the LED.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Cree, Inc.
    Inventors: David N. Randolph, Ryan C. Mohn
  • Patent number: 10734363
    Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, a light extraction surface of each substrate portion includes protruding features and light extraction surface recesses. Lateral borders between different pixels are aligned with selected light extraction surface recesses. In some aspects, selected light extraction surface recesses extend through an entire thickness of the substrate. Other technical benefits may additionally or alternatively be achieved.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 4, 2020
    Assignee: CREE, INC.
    Inventor: Peter Scott Andrews
  • Patent number: 10720379
    Abstract: The base of an integrated circuit package comprises a first side, and a second side opposing the first side. The base further comprises, a base mounting section, a die mounting section, and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises an opening extending through the base from the first side to the second side. At least a portion of the recess intersects with the opening.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 21, 2020
    Assignee: CREE, INC.
    Inventors: Sung Chul Joo, Bradley Millon, Erwin Cohen
  • Patent number: D890961
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: July 21, 2020
    Assignee: Cree, Inc.
    Inventors: Jesse Colin Reiherzer, Colin Kelly Blakely, Samuel Richard Harrell, Jr., Erin R. F. Welch, Roshan Murthy
  • Patent number: D892066
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 4, 2020
    Assignee: Cree, Inc.
    Inventors: Jesse Reiherzer, Jeremy Nevins, Joseph Clark