Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

Abstract: A full-duplex communication device includes a transmit channel, a receive channel, and echo cancellers connected between the transmit channel and the receive channel. A plurality of control parameters and status indicators are defined for both channels. The plurality of control parameters are accessed via a writable interface for controlling operations of the communication device. Typically the control parameters are modified, enabled, and disabled based on an implemented control method and based on signal conditions, including noise, echo, tone, and other abnormal noise conditions. A writable access port enables a user to request tweaking, modification, enabling, and disabling of multiple features and controls. A readable/writable access port enables access to multiple status parameters that are indicative of the status of the communication device and channel operating conditions.

Abstract: A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.

Abstract: A nonperiodic waveform is forced to a periodic character to facilitate looping of the waveform without introducing audible, and thus objectionable, sound artifacts. Nonperiodic waveforms are typically nonperiodic due to the presence of nonharmonic high frequency spectral components. In time, the high frequency components decay faster than low frequency components and looping of the waveform is facilitated. A loop forcing process and loop forcing filter facilitate looping of a nonperiodic waveform by accelerating the removal of the nonperiodic high frequency components. A loop forcing filter accelerates the removal of nonperiodic high frequency components using a comb filter having a frequency selectivity that varies in time.

Abstract: Early reflection and reverberation processing using a decimating filter simulates the high frequency attenuation of an actual physical and acoustical environment and advantageously reduces the memory storage and computational burden of the early reflection and reverberation processing method. A method of generating a reverberation effect in a sound signal includes decimating the sound signal in the sound signal path and forming an early reflection sound signal from the decimated sound signal. The early reflection sound signal has a reduced sample rate an attenuated high frequency components in comparison to the sound signal.

Abstract: A dynamic volume control system in an audio processor uses gain and delay signals from a digital signal processor to dynamically control the user-selected volume of the audio processor. The digital signal processor executes audio signal processing operations that affect the gain applied to the audio signal so that the signal gain inherent in the signal processing path is known. The digital signal processor transfers the known gain and a predicted group delay signal to the dynamic volume control system to dynamically adjust the user-selected volume of the system. The digital signal processor is integrated with a digital-to-analog converter (DAC) in a dynamic volume control system that exploits the known gain and group delay to perform DAC volume control.

Abstract: A method of processing exponent data in an audio decoder. A first block of audio data is received including encoded exponent data. The encoded exponent data is packed into packed encoded words and stored in memory. Exponents are generated from the packed encoded words in memory for processing the first block of audio data. A second block of audio data is received. A determination is made as to whether a reuse flag has been set for the second block, and if the reuse flag has been set, exponents are generated from the packed encoded words memory for processing the second block of data.

Abstract: A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.

Abstract: A sound or music synthesizer includes a reverberation simulator having a substantially reduced volatile storage, random access memory, or buffer size in comparison to conventional reverberation simulators by decimating the sound signal prior to applying the sound signal to a reverberator and then interpolating the sound signal generated by the reverberator to restore the sample frequency. The substantial reduction in buffer size enables the usage of the reverberator in low-cost, reduced size and single-chip environments.

Abstract: A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration).

Abstract: A linear approximation to an exponential decay function exploits the characteristic of an exponential function that, at equal time intervals, the ratio of a parameter value at the beginning of the interval to the parameter value at the end of the interval remains constant. The technique for linear approximation of an exponential decay includes selection of a constant period or interval of time and selection of a constant ratio between the parameter value at the beginning of the constant period and the parameter value at the end of the constant period. In one embodiment, the selected ratio is one-half to exploit a binary arithmetic implementation. For a ratio of one-half, the exponential decay has a "half-life" in which only half the parameter value at the beginning of a period is left at the end of the selected "half-life time period".

Abstract: A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56).

Abstract: A high pass filter is provided utilizing a digital filter with coefficients that can be switched to provide for two responses, a fast response and a slow response. A first response is provided by an accumulator block (38) disposed between the output and a summing junction (30) on the input of the digital filter. A multiplexer (40) selects between this accumulator block (38) and a slow response accumulator block (42). The switching is effected with a zero crossing detect circuit (26). When the first and faster response brings the DC level down to a value that is close to zero, the second and slower response is selected to basically lock it to zero.

Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream.

Abstract: A very high gain cascode amplifier includes a cascoded differential structure wherein a cascoded N-channel leg comprised of two series connected transistors (56) and (58) are connected between an output node (30) and ground with a corresponding P-channel cascode leg comprised of series connected P-channel transistors (38) and (40) connected between node (30) and V.sub.DD. Transistor (58) is connected to bias voltage, with transistor (56) having a gate thereof connected to a bias circuit (72) which provides gain thereto to increase the gain of a cascoded leg while not introducing any error into the amplifier. The bias circuit (72) has an imbedded structure that sets the gate voltage of transistor (56) to a voltage equal to one threshold voltage plus twice the V.sub.on voltage of transistors (56) and (58).

Abstract: The present invention relates to a tone signal generator. The tone signal generator includes first tone signal generation means for producing a dual-tone, multi-frequency ("DTMF") audio signal; second tone signal means for producing a plurality of non-DTMF audio signals; storage means for storing data that represents at least one channel of an output audio tone signal; and selection means for selectively loading the DTMF signal into the storage means and for selectively accumulating the non-DTMF signals into the storage means so as to generate the output tone signal.

Abstract: A frequency modulation (FM) tone signal generator for generating a FM tone signal is disclosed. The tone signal generator includes a waveform generator having a plurality of wave tables, a selector and an enveloper. The waveform generator furnishes a waveform signal in response to a phase angle address signal. Each wave table stores a different waveform. The selector selects one of the wave tables in response to a plurality of selection signals such that the selected wave table largely provides the waveform signal upon being addressed largely by the phase angle address signal. Selection of the selected wave table varies with each selection signal. The enveloper impresses an envelope signal on the waveform signal. The envelope signal is used as a carrier or modulator for generating the FM tone signal.

Abstract: An algorithmic converter system includes an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting the redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to the loop gain, wherein the redundant digital code specifies coefficients of the polynomial. The redundancy extends the analog input conversion range with respect to the voltage reference of the algorithmic converter. Moreover, if the algorithmic converter has a maximum offset of V.sub.offmax, a reference voltage of V.sub.ref, and a loop gain less than 2/(1+V.sub.offmax /V.sub.ref), then loop offset will not cause differential nonlinearities. Nonlinearity is further reduced by digitally compensating for variations in the loop gain.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: A frequency modulation (FM) tone signal generator for generating a FM tone signal is disclosed. The tone signal generator includes a waveform generator having a plurality of wave tables, a selector and an enveloper. The waveform generator furnishes a waveform signal in response to a phase angle address signal. Each wave table stores a different waveform. The selector selects one of the wave tables in response to a plurality of selection signals such that the selected wave table largely provides the waveform signal upon being addressed largely by the phase angle address signal. Selection of the selected wave table varies with each selection signal. The enveloper impresses an envelope signal on the waveform signal. The envelope signal is used as a carrier or modulator for generating the FM tone signal.