Patents Assigned to Cypress Semiconductor Corporation
  • Patent number: 11119548
    Abstract: Technology to dynamically throttle power in a power delivery system is described. In one embodiment, a power delivery system includes a controller associated with a port to supply power. The controller manages a power budget available to the port based on a current state of one or more system parameters. The power budget available to the port can be throttled when the power delivery system operates under stress conditions and adjusted when the power delivery system is no longer operating under stress conditions.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ajay Venkideswaran, Debraj Bhattacharjee, Kailas Iyer
  • Patent number: 11119602
    Abstract: A touch screen display and corresponding devices and methods are disclosed, the touch screen display comprising a touchscreen having a plurality of capacitive sensors and a passive dial having one or more conductive elements, the passive dial mounted within an active area of the touchscreen such that the one or more conductive elements are proximate to the face of the touchscreen and move in conjunction with a rotation of the passive dial. The touch screen display may further include a touchscreen controller to detect an angle of the passive dial using conventional capacitive sensing techniques.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andriy Yarosh, Jens Weber
  • Patent number: 11121635
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side IC controller of the AC-DC converter includes a SR-SNS pin coupled to a peak-detector block, a zero-crossing block, and a calibration block. The calibration block is configured to: measure a loop turn-around delay (Tloop), a time (Tpkpk) between two successive peak voltages detected on the SR-SNS pin, and a time (Tzpk) from when the voltage sensed on the SR-SNS pin crosses zero voltage to when a peak voltage is detected on the SR-SNS pin; and set timing for a signal to turn on a power switch in a primary side of the AC-DC converter based at least on Tloop, Tpkpk, and Tzpk.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai
  • Patent number: 11115068
    Abstract: A system for data-based pre-distortion for a nonlinear power amplifier includes a digital pre-distortion (DPD) component, including a DPD processor and a DPD calibration engine, where the DPD processor applies a set of DPD coefficients to a digital baseband data signal, to generate a pre-distorted digital baseband data signal for conversion to a radio frequency (RF) signal and amplification by a nonlinear power amplifier (PA) to generate an RF output signal, where the DPD calibration engine compares a digitized, down-converted version of the RF output signal with the digital baseband data signal, to determine distortion coefficients of the nonlinear PA, and to update the set of pre-distortion coefficients in the DPD processor to compensate for the distortion coefficients of the non-linear PA, where data transmission is uninterrupted by the transmission of non-data calibration signals.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 7, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sudhir Kumar Kasargod, Ayush Sood, Kempraju G
  • Patent number: 11113497
    Abstract: A capacitive fingerprint sensor includes a set of capacitive sensor electrodes in a sensing area. The set of capacitive sensor electrodes includes a set of transmit (Tx) sensor electrodes, a set of receive (Rx) sensor electrodes, and a set of compensation electrodes. The fingerprint sensor also includes a multiphase capacitance sensor that is configured to perform a sensing scan of the capacitive sensor electrodes by applying a first Tx signal to a first subset of the Tx sensor electrodes while simultaneously applying a second Tx signal to a second subset of the set of Tx sensor electrodes, and based on a compensation signal received at the set of compensation electrodes, reduce a component of the Rx signal originating from a source other than a contact at the sensing area.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 7, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Kravets, Oleksandr Hoshtanar, Hans Klein, Oleksandr Karpin
  • Patent number: 11114945
    Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rashed Ahmed, Hariom Rai
  • Patent number: 11109394
    Abstract: A method can include, in an access point (AP) configured to control data transfers for associated stations (STAs) in time intervals, storing a unique identifier and quality-of-service (QoS) requirement for each STA of a first set in a nonvolatile memory of the AP. In response to a STA associating with the AP, if the associating STA is in the first set, allocating time for the STA in the time intervals to meet the QoS requirement of the STA without receiving transmitted QoS data from the STA, and if the associating STA is not in the first set, establishing a QoS for the STA having a lower priority than any associated STAs of the first set. Corresponding systems and devices are also disclosed.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 31, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hui Luo, Xianmin Wang, Hongwei Kong
  • Patent number: 11105851
    Abstract: A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold Kutz, Timothy John Williams, Bert Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
  • Patent number: 11106604
    Abstract: Example apparatus, systems, and methods receive a request for data associated with an address and responsively access a memory array to obtain the data. Embodiments transition a bus from a first state to a second state and after the transitioning of the bus, drive the data onto the bus.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 31, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventor: Clifford Zitlaw
  • Publication number: 20210266808
    Abstract: Systems, methods, and devices seamlessly playback data files using one or more wireless connections. Methods include establishing a first wireless connection between a source device and a sink device, the first wireless connection using a first transmission protocol and transmitting audio data via the first wireless connection. Methods further include determining a switch should be initiated based on one or more signal quality metrics, the one or more signal quality metrics representing, at least in part, an estimate of a quality of the first wireless connection. Methods also include switching to a second wireless connection between the source device and the sink device, the second wireless connection using a second transmission protocol, and the second wireless connection using data packets encapsulated for transmission in accordance with the second transmission protocol.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 26, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Krishna Kishore Avadhanam, Ashish Kumar Malot, Robert Zopf
  • Publication number: 20210263878
    Abstract: A dual-integrated gate-driver with reverse current protection (RCP) fault protection is described. A Universal Serial Bus Type-C (USB-C) controller includes a first terminal, a second terminal, and a dual-gate driver. The dual-gate driver drives a first power field effect transistor (FET) coupled to the first terminal and a second power FET coupled to the second terminal. The first power FET and the second power FET are connected in series between a voltage bus (VBUS_C) terminal of a USB Type-C connector and a voltage supply to deliver power to the VBUS_C terminal. A breakdown voltage of each of the first power FET and the second power FET is less than 20 volts. The dual-gate driver controls the first power FET and the second power FET in response to at least one of a short circuit event or a reverse current event.
    Type: Application
    Filed: June 25, 2020
    Publication date: August 26, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hemant P. Vispute, Ramakrishna Venigalla, V.M. Saravanan
  • Patent number: 11100034
    Abstract: A dual-integrated gate-driver with reverse current protection (RCP) fault protection is described. A Universal Serial Bus Type-C (USB-C) controller includes a first terminal, a second terminal, and a dual-gate driver. The dual-gate driver drives a first power field effect transistor (FET) coupled to the first terminal and a second power FET coupled to the second terminal. The first power FET and the second power FET are connected in series between a voltage bus (VBUS_C) terminal of a USB Type-C connector and a voltage supply to deliver power to the VBUS_C terminal. A breakdown voltage of each of the first power FET and the second power FET is less than 20 volts. The dual-gate driver controls the first power FET and the second power FET in response to at least one of a short circuit event or a reverse current event.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 24, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hemant P. Vispute, Ramakrishna Venigalla, V. M. Saravanan
  • Patent number: 11101673
    Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 24, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Hamid Khodabandehlou, Sumeet Gupta, Syed Raza, Anup Nayak
  • Publication number: 20210255727
    Abstract: Described herein are devices, methods, and systems that detect the presence of faults such as shorts and/or opens within a touch sensitive display panel. In one embodiment, a touch screen controller is disclosed, the touch screen controller comprising one or more receive channels, where each receive channel is configured to scan a corresponding group of sensors of a plurality of sensors. The touch screen controller may also comprise a plurality of multiplexers, each multiplexer configured to selectively couple a respective sensor of the plurality of sensors to a corresponding receive channel or a reference voltage. The touch screen controller may further comprise a processing device configured to detect one or more shorts based on DC current sensing. The touch screen controller may also detect one or more opens based on AC current sensing of each of the one or more receive channels.
    Type: Application
    Filed: September 21, 2020
    Publication date: August 19, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Oleksandr Pirogov, Viktor Kremin, Vadym Grygorenko, Jens Weber
  • Patent number: 11093078
    Abstract: Disclosed are sensing systems and methods that eliminate CPU intervention or interrupts when performing sensor scans of a touch interface, supports low power sensing operation without requiring periodic wake up of the CPU, and is scalable to multi-channel or multi-chip sensor configuration to support large touch screens or a high number of sensors. A sensor scanning module may operate in a chained-scan using direct memory access (CS-DMA) mode or an autonomous scan-multiple scan (AS-MS) mode to perform scanning of all sensors within a frame without requiring CPU intervention or generating CPU interrupts after every scan in the frame. The sensor scanning module may operate autonomously in a low-power always-on scan (LP-AOS) mode for multiple frames without CPU interaction until a touch event is detected. The CPU may operate in a low power sleep mode during the scan while providing consistent refresh rate and low touch-to-system wake up latency.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vibheesh Bharathan, Andrew Kinane
  • Publication number: 20210247484
    Abstract: Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.
    Type: Application
    Filed: March 4, 2021
    Publication date: August 12, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chihning Chen, Chung-Yen Huang, Wen-Tong Kuo
  • Patent number: 11088692
    Abstract: A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 10, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • Publication number: 20210240249
    Abstract: A power supply architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller comprises a VCONN pin, a power rail coupled to internal circuits of the IC controller, and a VCONN switch coupled between the VCONN pin and the power rail. The VCONN switch comprises: a drain-extended n-type field effect transistor (DENFET) coupled between the VCONN pin and the power rail; a pump switch coupled to a gate of the DENFET; a resistor coupled between the VCONN pin and the gate of the DENFET; and a diode clamp coupled between the gate of the DENFET and ground.
    Type: Application
    Filed: January 20, 2021
    Publication date: August 5, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Nicholas Alexander Bodnaruk, Anup Nayak, Pavan Kumar Kuchipudi
  • Patent number: 11082449
    Abstract: Disclosed are systems and methods for diagnosing the health of a plurality of memory cells in a memory array. Diagnostics are initiated from a remote server via an encrypted channel on the memory device embedded in an end-use system. The memory device includes a plurality of memory cells in a memory array. At the remote server, encrypted diagnostics data is received in response to execution of a diagnostics program by the memory device on the plurality of memory cells. The diagnostics data pertains to the health of the memory cells. The encrypted diagnostics data is decrypted into decrypted diagnostics data and the decrypted diagnostics data is analyzed to determine the health of the memory cells. Failure mitigation is performed for the memory device if the analyzing indicates unhealthy memory cells.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 3, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wen-Ching Chou, Sandeep Krishnegowda, Qamrul Hasan
  • Patent number: 11081194
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: August 3, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh