Abstract: Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.

Abstract: A method and system for controlling the processing of an IC chip assembly line using a central computer system and a common communication protocol. In one embodiment, a manufacturing execution system (MEM) is used as the computer system and the communications protocol is the standard semi equipment communications standard/generic equipment model (SECS/GEM). One or more equipment cell controllers (CC) may be used to communicate between the MES a plurality of in-line substations which comprise the assembly line. Automated vision camera systems may also communicate information to the MES via the CCs. In one embodiment, the MES maintains a database in memory comprising processing history of a die-strip and results of automated die-strip examination from the vision camera systems. In one embodiment, the die-strip may be of a ball grid array (BGA) type.

Abstract: A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device.

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract: A decoder circuit (100) is disclosed that may include “string” decoders (102-0 and 102-1), a compare circuit (104) and an enable circuit (106). String decoders (102-0 and 102-1) may provide “one-hot” or “string” decoding. One-hot decoding may activate one pre-decode signal. String decoding may activate one or more pre-decode signals. A compare circuit (104) may receive at least two pre-decode signals from one string decoder (102-1) and compare such values to generate a comparison result CMP. An enable circuit may generate decoder output signals (DEC0-DEC(n?1)) according to a comparison result CMP.

Abstract: A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.

Abstract: An apparatus comprising one or more look-up-tables (LUTs). The LUTs may be configured to provide logical functions. The one or more LUTs are generally implemented within a multiport memory.

Abstract: A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.

Abstract: A system and method for graphically displaying global resources and their associated parameter values and apply the global resources across multiple design projects. The system and method also provide a graphical interface which displays the possible parameter values of an associated global resource. This graphical interface utilizes pop up menu to for viewing the possible parameter values and the selection of the current parameter value. The system and method also provide tracking and updating of the hardware resources which utilize the parameter values of the global resources. Further, the system also allows the storage of these parameters values of the global resources. By storing these parameter values of the global resources, these parameter values can be set as default global settings. These default global settings can be recalled and associated with different projects without manual entry of the parameter values.

Abstract: Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.

Abstract: The present invention is a system and method of facilitating automatic generation of the source code in a convenient and efficient manner. In one embodiment of the present invention, a programmable system on a chip (PSoC) boot file generation method is utilized to create a boot file. A boot template file is created comprising special symbolic variable names that point to configuration registers within a programmable system on a chip (PSoC). User module selections are received with delineation of preferred configurations and functions associated with components of said programmable system on a chip (PSoC). Application files are automatically generated based upon user selections of PSoC configurations and functions. The special symbolic variable names are substituted or replaced with actual configuration register names. In one embodiment, a present invention programmable system on a chip (PSOC) boot file generation method also facilitates providing interrupt processing routines to the appropriate vector.

Abstract: A programmable logic device, a memory device and a microcontroller manufactured on a single integrated circuit chip. In one example, the programmable logic device may comprise one or more macrocells each comprising an input/output macrocell or a buried macrocell. In another example, the programmable logic device may be a complex programmable logic device (CPLD) or a programmable logic array (PLA).

Abstract: A method for forming a magnetic tunneling junction (MJT) is provided. In some embodiments, the method may include patterning one or more magnetic layers to form an upper portion of a MTJ. The method may further include patterning one or more additional layers to form a lower portion of the MTJ. In some cases, the lower portion may include a tunneling layer of the MTJ having a width greater than the upper portion. In addition, in some embodiments the method may further include patterning an electrode below the lower portion. In some cases, the electrode may include a lowermost layer with a thickness equal to or less than approximately 100 angstroms. In addition or alternatively, the electrode may have a width greater than the width of the tunneling layer. In yet other embodiments, the method may include forming spacers along the sidewalls of the upper and/or lower portions.

Abstract: A system and method is provided herein to fabricate openings in a semiconductor topography using feed forward control of etch process parameters. In one embodiment, a method includes measuring one or more dimensional features of a semiconductor topography to obtain pre-etch values. The method also includes determining a statistical result of the pre-etch values and adjusting one or more processing parameters if the statistical result is less than a target value. Subsequently, the method includes etching the semiconductor topography based upon the statistical result to form one or more openings in the semiconductor topography. As such, the system and method described herein fabricates openings using feed forward control of the etch process parameters to compensate for structural variations within semiconductor topographies that may exist between wafer-to-wafer and/or between lot-to-lot.

Abstract: A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to wake-up the second circuit in response to an input signal. The input signal generally comprises a programmable delay value.

Abstract: Embodiments of the present invention relate to a switched-capacitor filter which comprises a first stage which itself comprises a first switched capacitor, a second stage which itself comprises a second switched capacitor, a switched capacitive element that couples the output of the first stage to the input of the second stage, and a non-switched capacitive element coupled from the output of the second stage to the input of the first stage to provide damping of the switched-capacitor filter. Both stages are implemented as inverting analog amplifiers and the filter is especially well suited to semiconductor manufacture. The switched capacitor filter is implemented as part of a user module in a programmable system on a chip, or PSoC.

Abstract: A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

Abstract: Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 ? of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 ?/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.