Abstract: An apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level that is independent of the control signal.

Abstract: An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be configured to provide a readback of an internal address value when in a first state and a readback of a mask value when in a second state.

Abstract: A CMP system, a wafer carrier, and components of a wafer carrier are provided for processing a semiconductor topography. In particular, a CMP system, a wafer carrier, and components of a wafer carrier are provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the semiconductor topography may include any region of the topography. The wafer carrier components may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of the semiconductor topography than in a second portion of the semiconductor topography.

Abstract: An assembly for holding a substrate is provided. The substrate has a first surface, a second surface, opposite the first surface and an outer peripheral portion. The assembly includes a holding body having a support surface for supporting the substrate. The holding body has an aperture for passing therethrough a gas having a thermal conductivity. Additionally, the assembly includes a heat transferring seal having a first surface for frictionally engaging the second surface of the substrate. The heat transferring seal has a second surface, opposite the first surface, for frictionally engaging the support surface of the holding body. The heat transferring seal also has an inner peripheral portion defining an opening for receiving the gas. The heat transferring seal has a thermal conductivity closely matched with the first thermal conductivity of the gas for providing substantially uniform heat transfer across the substrate.

Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.

Abstract: A data driven method and a system for monitoring resource usage for programming a microcontroller. The microcontroller design system includes a configuration and design system with integrated datasheet information and having three independent, but integrated workspaces to provide a programmer an organized way of displaying configuration and design information. The three workspaces include a user module selection workspace, a user module placement workspace and a user module pin out workspace for allowing the programmer to select desired function components for a target microcontroller device. The configuration and design system includes data files that specify hardware resources that are tracked as the designer selects user modules to program the microcontroller. Resource usage values are cumulatively tracked and displayed interactively in a resource manager workspace to enable the designer to keep constant track of the type of resources and the amount of resources used.

Abstract: An input buffer circuit has a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier.

Abstract: An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Abstract: A circuit that may be configured to detect a lockout condition of a phase lock loop (PLL) circuit. The circuit may be configured to forcibly correct an operating frequency of the PLL circuit.

Abstract: An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal in response to an address signal and a counter control signal. The generation circuit may (i) comprise an internal counter register and (ii) be configured to generate an output address in response to the mask signal, the unique counter control signal, and the incremented state signal. The mask signal may be configured to selectively mask the internal counter register.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in response to an adjustable balance point of the input request signals, where the balance point is adjusted to reduce a metastable state of the first circuit.

Abstract: Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.

Abstract: A switch for at least two clock domains, comprising (a) first and second synchronizers in a first clock domain, (b) third and fourth synchronizers in a second clock domain, and (c) a state machine configured to interface with said synchronizers, thereby controlling switching between said first and second clock domains.

Abstract: A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

Abstract: A decoupling circuit comprising a first capacitor, and a first current mirror coupled to the capacitor, wherein the first current mirror is configured to multiply the capacitance effect of the first capacitor is disclosed. The first current mirror may comprise a first transistor, and a second transistor coupled to the first transistor, wherein the second transistor is configured to amplify the current entering the first transistor. The first transistor and the second transistor may comprise n-channel MOSFET transistors. The decoupling circuit may further comprise a bias network coupled to the first current mirror, wherein the bias network is configured to bias the first current mirror. The bias network may comprise a p-channel MOSFET.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: The present invention is directed to an apparatus and method for low stress test modes. A method of performing a low stress test mode may include applying an initial voltage in an amount sufficient to perform a device burn-in to a first device and a second device. Voltage at the second device is reduced, wherein voltage is reduced at the second device while voltage at the first device is at an amount sufficient to perform device burn-in.

Abstract: One aspect of the invention comprises an apparatus comprising a frame for transmitting information via a network, comprising one or more packets of different data types and lengths located anywhere inside the frame. Another aspect of the present invention comprises a network configured to transfer a plurality of frames and one or more nodes coupled to the network. Each of the one or more nodes may be configured to receive and/or transmit one or more of the plurality of frames. Each of the plurality of frames may be configured to store one of a number of packets of different data types and different data lengths, anywhere within the frame.

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.