Abstract: A circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.

Abstract: A system for displaying statuses for multiple signal paths or ports on LEDs is disclosed. The system comprising a plurality of shift circuits receives a data signal comprising groups of status signals. The data signal is serially shifted from one shift circuit to another so as to parse the status signals to be displayed on appropriate LEDs designated for each of the signal paths or ports. As a result, multiple statuses can be effectively displayed in real time using a minimum number of LEDs.

Abstract: Embodiments of the invention describe a method and apparatus used to determine the position of a wiper on a potentiometer without the need for an external ADC. Two capacitors are each connected to an end of a potentiometer, and then are charged or discharged simultaneously by a current source or current sink attached to the wiper of the potentiometer. The time required for each of the capacitors to charge or discharge to a threshold voltage level is measured and subsequently used to determine the position of the wiper on the potentiometer.

Abstract: A semiconductor device that includes an integrated circuit and an HBM structure formed on different semiconductor substrates is provided. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit and protection structures coupled to the input or output or input/output circuitry. In an embodiment, the integrated circuit may include input or output or input/output structures spaced across an area of the integrated circuit. The input or output or input/output circuitry of the HBM structure may be coupled to the input or output or input/output structures of the integrated circuit. A method for developing a design for an HBM structure is also provided. The method may include coupling an HBM structure formed on a first semiconductor substrate to an integrated circuit formed on a second semiconductor substrate. The method may also include testing the HBM structure and altering the HBM design based on the testing.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to the first control signal.

Abstract: According to one embodiment (300), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls (302). A first insulating layer may then be formed without first forming a liner (304), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures (306). Contact structures may then be formed (308).

Abstract: A method of performing memory operations of a memory device having precharge, read and write states is disclosed. The method includes refreshing the memory device provided a refresh timer expired and the memory device is in the precharge state. The method further includes entering the precharge state, refreshing the memory device and returning to the read state provided the memory device is in the read state for a predetermined period of time. The memory device is refreshed provided the memory device is transitioning from the read state to the write state and the refresh timer has expired.

Abstract: In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: An apparatus comprising a reference circuit, a correction circuit and an output circuit. The reference circuit may be configured to generate a bias signal. The correction circuit may be configured to correct a bias voltage of the bias signal. The output circuit may be configured to generate an output current in response to the bias signal. The bias signal may be corrected in response to the bias voltage.

Abstract: An apparatus comprising a delay line and a control circuit. The delay line may be configured to generate an output signal in response to an input signal and one or more control signals. The delay line may be self-clocked. A phase of the output signal may be adjusted in response to the one or more control signals. The control circuit may be configured to generate the one or more control signals in response to the input signal and the output signal.

Abstract: A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention process a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Abstract: A multi-chip integrated circuit assembly including embodiments having a plurality of integrated circuits connected thereto. According to one embodiment, a multi-chip assembly (100) may include a first surface (102) having first surface connections (106) and a second surface (104) having second surface connections (108). A first surface (102) may be lower than a second surface (104). First and/or second surface connections (106 and 108) may have conductive paths to one another and/or to assembly connections (110). In one particular arrangement, first and second surface connections (106 and 108) may provide “flip-chip” type connections to integrated circuits. Assembly connections (110) may provide a ball grid array (BGA) type connection for the multi-chip assembly (100).

Abstract: A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Abstract: The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

Abstract: A pulse generator. The pulse generator has a pseudo random number generator, a comparator coupled to the pseudo random number generator, and a register coupled comparator. The comparator performs comparisons of values generated by the pseudo random number generator and a value in the register, wherein the comparator outputs a pulse that is modulated according to the comparison. A low-pass filter may coupled to the comparator output and the register may receive samples of a digital signal. Low-pass filtering the comparator output implements a digital-to-analog converter that is less expensive than conventional delta-sigma modulator DACs and has better performance than conventional PWM DACs.

Abstract: An improved signaling system and method are provided that uses transconductance signaling rather than voltage or current signaling. A transient voltage applied to a first end of a conductor can produce a varying current placed into a low impedance node at a second end of the conductor. The second end is preferably pinned to a fixed voltage value, and the low impedance second end will allow current upon the second end to freely transition, enabling the conductor to arrive at a steady state condition much sooner than with conventional signaling methods. The present transconductance signaling method avoids large changes in voltage along the greater part of the conductor due to a current sent through this resistive conductor. This greatly improves transient behavior as, for example, evidenced by signal rise and fall times for digital signals produced by this transconductance signaling method.

Abstract: A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Abstract: A method and processor configured to handle an exception may employ a “retry” signal, which may be associated with a memory access attempt by the processor. The retry signal determines if an exception is to be serviced during a period in which the memory access is delayed. In one embodiment for which the exception is an interrupt, the retry signal is asserted when memory access is delayed and the processor may proceed to service an interrupt request during this period of delayed memory access, regardless of the degree of completion of an instruction by the processor. During a period of delayed memory access, the processor may suspend instruction execution until the memory access becomes available. Upon completion of servicing the interrupt, the processor may resume instruction execution beginning with the last instruction attempted before the suspension of the instruction execution due to the delayed memory access.

Abstract: Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch.