Abstract: This invention relates to a method of etching a bond pad in a semiconductor or integrated circuit, a method of using an etching apparatus and a semiconductor device.

Abstract: A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response to a second input signal and the control signal. The second driver circuit may be configured to generate a second output signal in response to the delay signal.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal.

Abstract: A circuit and method for synchronizing a data signal to one of a plurality of clocks. The clock may include (i) a pulse generator configured to generate two pulses separated by a delay, (ii) a clock generator configured to generate the plurality of clocks, and (iii) a logic circuit configured to select the clock for synchronizing the data signal.

Abstract: A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times other than when the active edge is propagating through the delay circuit. As a result, a reference generator with reduced power consumption is realized.

Abstract: A circuit comprising a first driver circuit, a second driver circuit and a delay circuit. The first driver circuit may be configured to generate a first output signal and a control signal in response to a first input signal. The delay circuit may be configured to generate a delay signal in response to a second input signal and the control signal. The second driver circuit may be configured to generate a second output signal in response to the delay signal.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices.

Abstract: A circuit for generating an output signal in response to an input signal that propagates over devices operating at various supply voltages. The circuit generally comprises a first device operating in a first voltage, a second device operating in a second voltage and a clamp device coupled to each of the first and second devices. The clamp device generally operates at the second supply voltage, which may cause the output signal to be propagated through the circuit with a minimum distortion.

Abstract: A circuit and method for deskewing signals by using cross power supply logic paths to compensate for delays created by power supplies operating at different voltages. A first replica circuit operating at a first supply voltage is placed in series with a first signal operating at a second supply voltage. A second replica circuit operating at the second supply voltage is placed in series with a second signal having a skew difference from the first signal and operating at the first supply voltage. The replica circuits generally have a scale factor which is generally a fraction of the equivalent driver circuits associated with the particular output signals. As a result, the present invention will deskew arbitrary power supply differences. By matching delays, the replica and true circuits provide the same delay. As a result, the sum of the delays for all the blocks in each path will be constant which maintains a desired skew difference between the output signals.

Abstract: The present invention concerns a process that maintains a second (or "replica") set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or "replica") alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be "printed" in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an "open frame" process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

Abstract: The present invention concerns a circuit and method for improving the data access times across boundary reads between cascaded buffers, such as FIFOs, that are connected to a common data output bus. The circuit allows read accesses within a cascaded buffer system to have similar access speeds, i.e., a boundary read is not noticeably slower or faster than any other non-boundary read access from an individual buffer in the system. The circuit may not adversely affect the data sheet or operating system parameters, and imposes minimal chip real estate constraints.

Abstract: The invention relates to a method of forming a non-volatile memory device with a ramped tunnel dielectric layer, in which a floating gate material layer is being oxidized such that a tunnel dielectric layer is formed having a thickness at a drain region edge which is greater than a thickness at a source region edge.

Abstract: A novel method and apparatus for testing a device is described. The novel method and apparatus uses a reduced number of method steps, instructions, and clock cycles in order to test a device. In one embodiment of the present invention, a method for testing a device is described in which a device is instructed in one instruction to receive address information and a first data packet. The address information and the first data packet are loaded into the device. The first data packet may be selectively passed through a first storage element into a second storage element, and the address information may be loaded into the first storage element. The device is then instructed to program the first data packet into an address location of said device defined by the address information stored in the device. The device is then instructed to read or capture a second data packet from the address location defined by the address information. The second data packet is then output from the device.

Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V.sub.control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V.sub.control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V.sub.control.

Abstract: A memory controller is disclosed for use in physically mapping a VESA Unified Memory Architecture (VUMA) device, Row Address Strobe signal RAS# to a selected one of a plurality of memory banks. The RAS# signal from the VUMA device is routed to the memory controller, not the memory bank directly. The memory controller employs a network of pass gates to provide an electrically-conductive channel for routing the VUMA device RAS# signal to the appropriate memory bank. The appropriate pass gate is caused to become conductive through the use of a decoder, and a 3-bit clocked register bank. The register bank is programmable to generate a select signal on its output that is representative of the desired memory bank to receive the VUMA device RAS# signal. The select signal, which is a 3-bit signal, is provided to the decoder, which activates one of its plurality of output lines to thereby cause the selected pass gate to conduct.

Abstract: A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches having a first complementary differential current switch and a second complementary differential current switch, the two sets of complementary differential current switches are connected in a push pull arrangement. In this arrangement, the outputs of the first complementary differential current switch of the first set of complementary differential current switches and the first complementary differential current switch of the second set of complementary differential current switches are connected with the input of the second complementary differential current switch of the first set of complementary differential current switches.

Abstract: An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: A high speed digital tester module for functionally testing integrated circuits while operating at very fast speeds or under real time conditions. The high speed digital tester captures data streams from the integrated circuit at a first frequency and inputs the data into a memory device at a second frequency, which is slower than the first frequency. The digital tester module comprises a phase locked-loop, a serial-to-parallel converter and an output memory device. The phase locked-loop captures the data stream from the integrated circuit and generates two clock signals, a bit-rate clock signal and a divide-by-N-clock signal. The parallel-to-serial converter clocks in the data stream in response to the bit-rate clock signal and converts the data stream into parallel data. The output memory device clocks in the parallel data in response to the divide-by-N clock signal.