Abstract: A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from both the internal domain and the external domain in a single view of the design interface.

Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

Abstract: Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage than the power supply and to provide power to the first charge pump during an active mode of the flash memory array.

Abstract: In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

Abstract: Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the timing; and transmit the captured value as an output data signal over the CXPI bus.

Abstract: An example apparatus uses a transceiver to determine a first attribute value of a first RF signal received through a first antenna during a first period. An attribute estimator determines a second attribute value of the first RF signal received through a second antenna during the first period. Responsive to a control signal, the apparatus switches the attribute estimator from being coupled to the second antenna to being coupled to a third antenna. The apparatus then uses the transceiver to determine a first attribute of a second RF signal received through the first antenna during a second period and uses the attribute estimator determine a second attribute of the second RF signal received through the third antenna during the second period. The apparatus then can estimate an angle of arrival associated with the first and second RF signals based on the first and second attributes of the first RF signal and the first and second attributes of the second RF signal.

Abstract: Calibrating a Gaussian frequency-shift keying modulation index includes generating a training sequence of bits, shaping a pulse from the training sequence according to an initial modulation index, and converting the shaped signal to a transmission signal. The transmission signal is then either looped through a radio frequency core or processed by frequency deviation estimation hardware to determine a frequency deviation. The frequency deviation is converted to a new modulation index, and potentially a ratio between a target modulation index and a measured modulation index as a scaling factor. The process is then iteratively repeated until a threshold frequency deviation is achieved.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

Abstract: An sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The sense unit may include an inductive coil. The sense unit may include a first capacitor. The inductive coil and the first capacitor are coupled in parallel between the first node and ground. In a second mode, a third signal is received at the first terminal and a fourth signal is output on the second terminal.

Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Abstract: A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.

Abstract: An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance sensing circuit also includes a comparator configured to generate an output based on comparing a first voltage of the first modulation capacitor with a second voltage of the second modulation capacitor, and initiate a transition between the first phase and the second phase in response to the comparing.

Abstract: An apparatus for inductive sensing or capacitive sensing is described. The apparatus may include a signal generator to output on a first terminal a first signal in a first mode and a second signal in a second mode. The apparatus may include a charge measuring circuit to receive on a second terminal a third signal in the first mode and a fourth signal in the second mode. The third signal is representative of an inductance of a sense unit coupled between the first terminal and the second terminal. The fourth signal is representative of a capacitance of the sense unit.

Abstract: A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a sense-amplifier coupled to the bit-line and reference line, and a processing-element configured to issue control signals to WL1, WL2, the plateline and the sense-amplifier. The cell is configured and operated to generate a bit-level reference in which a first voltage pulse is applied to the plateline during a read cycle for the data pulse and a second voltage pulse serves as a reference pulse and as a clear pulse.

Abstract: A memory device that includes a pair of non-volatile memory cells, a first memory cell including a first memory gate and a first select gate, and a second memory cell including a second memory gate and a second select gate. The first and second memory cells share a source line, and the first and second memory gates are not connected to one another.

Abstract: An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device. The host includes decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance of one or more capacitors sensed by the processing device.