Abstract: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

Abstract: A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract: Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.

Abstract: A fingerprint sensor-compatible overlay which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. In one embodiment, the overlay is configured to enclose a device which includes a fingerprint sensor. In another embodiment, the overlay is configured as a glove. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.

Abstract: A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.

Abstract: A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.

Abstract: Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.

Abstract: Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders.

Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.

Abstract: A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an offset voltage Voffset which becomes smaller depending on the ON period Ton in excess of ½ of an operating cycle T, to a coil current waveform Vsense.

Abstract: A method of processing a wafer in a production tool includes receiving a wafer at a process tool, the wafer associated with a wafer process history, acquiring data associated with wafers processed by the process tool and having the wafer process history, when the amount of acquired data is insufficient, acquiring additional data associated with wafers processed by the process tool and having a process history differing from the wafer process history by a single factor, when the amount of acquired data is sufficient, determining a process parameter using the acquired data, and processing the wafer with the production tool using the process parameter.

Abstract: An integrated circuit (IC) device can include at least one phase or delay lock loop (P/DLL) circuit comprising a plurality of circuit sections, at least one of the circuit sections responsive to digital calibration values to alter at least one periodic output signal; a nonvolatile memory (NVM) circuit formed in the same IC package as the at least one P/DLL circuit and configured to store the calibration values; and a processing circuit formed in the same IC package as the at least one P/DLL circuit and the NVM circuit, the processing circuit configured to generate the calibration values in response to target values and output values from the at least one P/DLL circuit, and to store the calibration values in the NVM circuit.

Abstract: A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command transfer request when in the second operation mode where after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.

Abstract: A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

Abstract: Techniques that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. In an example embodiment, a method of operating a memory device comprises monitoring on the power supply level applied to the device and determining a corresponding number of bitlines that the device can activate at the same time, generating a control signal based on the number of bitlines, and using the control signal to activate a portion of the memory device corresponding to the determined number of bitlines.

Abstract: A crystal oscillator start-up circuit capable of reducing a start-up time of a crystal oscillator is disclosed. The crystal oscillator start-up circuit is provided with a crystal oscillation unit including a crystal oscillator, a converter and an external oscillator. The crystal oscillation unit generates an output signal corresponding to the impedance characteristic of the crystal oscillator. The converter converts the output signal of the crystal oscillation unit to a voltage signal. The external oscillator outputs to the crystal oscillation unit an oscillation signal whose frequency is adjusted by the voltage signal to approach a resonance frequency of the crystal oscillator.