Abstract: A method and apparatus for mixed wire bonding and staggered bonding pad placement. A first plurality of bonding pads is arranged on a semiconductor device. A second plurality of bonding pads is also arranged on the semiconductor device. The bonding pads of the second plurality of bonding pads are arranged in a staggered pattern, such that the first and second pluralities of bonding pads form one of a plurality of double rows of bonding pads on the semiconductor device.

Abstract: An adjusting apparatus sets a designated value of a current source circuit to be a predetermined value, and causes discharging of a capacitor to end by switching a switch to a discharging side when the capacitor is not being charged by current output from a switching power source circuit. After the discharging of the capacitor ends and the designated value is set, the adjusting apparatus causes the capacitor to be charged by switching the switch to a charging side. The adjusting apparatus further measures a time period from the time when the switch is switched to the charging side until an electric potential difference of the capacitor exceeds a threshold value. Based on the measured time period and the predetermined value, the adjusting apparatus calculates the designated value such that the measured time period is a predetermined time period.

Abstract: Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.

Abstract: A capacitance sensing module includes a timer circuit configured to generate a repetitive trigger signal, a low power oscillator block configured to generate a clock signal having a higher frequency than the repetitive trigger signal, a sensing block coupled with the timer circuit and the oscillator block and configured to, in response to the repetitive trigger signal, detect a presence of a conductive object at a capacitive sensor button by applying an excitation signal based on the clock signal to the capacitive sensor button, and a wake logic block coupled with the sensing block and configured to transition a processing unit from a low power consumption state to a high power consumption state in response to the sensing block detecting the presence of the conductive object at the capacitive sensor button.

Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.

Abstract: A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

Abstract: A wireless tracking device including a positioning system for determining a location of the device and a processor connected to the positioning system. The wireless tracking device further including a wireless radio connected to the processor for transmitting the location of the device across a wireless area network. A vehicle monitoring system including a sensor, a microcontroller configured to receive a sensor input from the sensor and determine a vehicle condition data, and a wireless transmitter in communication with the microcontroller. The wireless transmitter is configured to transmit the vehicle condition data to a remote data network access point. A method of monitoring a vehicle including determining a status of the vehicle, locating an available wireless data network access point, and transmitting the status of the vehicle though the access point.

Abstract: An apparatus and method of converting a capacitance measured on a sensor element to a digital value. The apparatus may include a matrix-scanning device including drive lines and sense lines. A sense element is located at an intersection of one of the drive lines and one of the sense lines. The apparatus also includes a modulation circuit coupled to the drive lines and the sense lines, and a switching circuit having first switches controlled by a clock. The modulation circuit is configured to measure a mutual capacitance on the sense element and to convert the measured mutual capacitance to a first digital value. The modulation circuit is configured to measure a self-capacitance on at least one of the drive lines and to convert the measured self-capacitance to a second digital value.

Abstract: Apparatuses and methods of driving barrier electrodes of a capacitive-sense array with an excitation signal are described. One apparatus includes a capacitance-sensing circuit coupled to a capacitive-sense array including multiple electrodes. The capacitance-sensing circuit includes multiple sensing channels. The capacitance-sensing circuit is operative to measure signals on a first subset of the multiple electrodes using the multiple sensing channels. Each of the sensing channels is selectively coupled to one of the first subset of electrodes. The capacitance-sensing circuit is further operative to drive a barrier electrode of the multiple electrodes with an excitation signal while measuring the signals on the first subset. The excitation signal is greater in magnitude than the measured signals. The barrier electrode is adjacent to an edge electrode of the first subset that is coupled to one of the sensing channels.

Abstract: Systems and methods for switching between voltages are provided. One system includes an output, first and second switches coupled to the output. The system also includes a first transmission gate coupled to the first switch and a second transmission gate coupled to the second switch. One method includes receiving, at the first transmission gate, a first pair of complementary voltages and receiving, at the second transmission gate, a second pair of complementary voltages. The method further includes selecting the smallest voltage amongst both pairs of complementary voltages and outputting a third pair of complementary voltages. In one method, the first pair of complementary voltages includes a first negative voltage and a positive voltage, the second pair of complementary voltages includes a second negative voltage and the positive voltage, and the third pair of complementary voltages includes the smaller of the first and second negative voltages and the positive voltage.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.

Abstract: An apparatus may include processing logic coupled with a force sensor input and a touch sensor input. The processing logic is configured to determine a relative force magnitude based on a force signal received at the force sensor input and a baseline measurement of the force sensor. The processing logic updates the baseline measurement in response to detecting that the touch signal indicates the absence of the one or more touches from the sensing surface.

Abstract: A control circuit comprises a power supply unit configured to generate a voltage to be supplied to a load by turning on and off a first switch in response to a drive signal and control a drive current of the load by turning on and off a second switch in response to a control signal, a first controller configured to perform a first PWM control of the drive signal, based on a measurement value of the drive current, a second controller configured to perform a second PWM control of the control signal, based on an external signal, and a synchronous controller configured to synchronize an on-period of one period of the control signal to he a multiple of one period of the drive signal. Further, in the control circuit, during the on-period of the control signal, an inductor current for generating the drive current is cut off for a portion of every period of the drive signal.

Abstract: Provided herein is a method of processing an electronic device including operating a processing chamber at a first temperature while a workpiece is being processed and removing the workpiece and a carrier holding the workpiece from the processing chamber while decreasing the temperature within the processing chamber to a second temperature significantly lower than the first temperature. The method also includes increasing the temperature within the processing chamber to a third temperature significantly greater than the second temperature and significantly less than the first temperature while the processing chamber has no workpiece or carrier within.

Abstract: Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element.

Abstract: A switch circuit and method is described. In one embodiment, the switch circuit is configured to couple each of a plurality of plurality of capacitive sense elements and a plurality of capacitance sensors in different modes. In a first mode, the switch circuit is configured to couple each of the plurality of capacitance sensors to a group of two or more of the plurality of capacitive sense elements. In a second mode, the switch circuit is configured to couple the plurality of capacitance sensors to individual ones of the two or more of the plurality of capacitive sense elements in one of the groups.

Abstract: A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip.

Abstract: Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface.

Abstract: An apparatus and method of converting a capacitance measured on a sensor element to a digital value. The apparatus may include a switching capacitor as a sensor element, a modulation circuit coupled to the sensor element, and a switching circuit having a plurality of switches controlled by a variable-period clock. The modulation circuit is configured to measure a capacitance on the sense element and to convert the measured capacitance to a digital value.