Patents Assigned to Design Systems, Inc.
  • Patent number: 11501049
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling coefficient associated with a controlled source of the circuit model. Embodiments may further include extracting a transmission line mode from the circuit model and linking the circuit model, at least one via, and the transmission line mode to an external circuit to generate a modeled system. Embodiments may also include solving the modeled system using a modified nodal analysis.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 15, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Feng Miao, Jing Wang, Zhen Mu, Xuegang Zeng
  • Patent number: 11501044
    Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 15, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shirin Farrahi, Yang Lu
  • Patent number: 11494540
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 8, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sourav Kumar Sircar, Alwin Gupta, Marc Heyberger, Manish Bhatia, Manish Garg
  • Patent number: 11483185
    Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 25, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sachin Ramesh Gugwad, Hari Anand Ravi, Aaron Willey, Thomas E. Wilson
  • Patent number: 11474844
    Abstract: Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 18, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Justin Schmelzer
  • Patent number: 11475192
    Abstract: Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host device without halting the execution of the hardware emulator. The software host device can receive the message indicative of the assertion failure event, and execute, asynchronously relative to the execution of the hardware emulator, at least one fail action instruction associated with the assertion failure event.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 18, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manik Chandra Roy, Rajiv Roy
  • Patent number: 11469769
    Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 11, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis-Francois Tanguay, Jean-Francois Delage, Guillaume Fortin
  • Patent number: 11467620
    Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 11, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yuhei Hayashi, Mitchell G. Poplack
  • Patent number: 11463094
    Abstract: Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 4, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventor: Mathieu Gagnon
  • Patent number: 11463284
    Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 4, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventor: Mathieu Gagnon
  • Patent number: 11461530
    Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: October 4, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mateus Paiva Fogaça, Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 11455450
    Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: September 27, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sushobhit Singh, Arvind Nembili Veeravalli, Naresh Kumar, Beenish, Mahesh Diwakar Sadhankar, Ankit Sethi
  • Patent number: 11449654
    Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: September 20, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nicholas Claude Warren, Matthew Noseworthy, Liam Cadigan, Darryl Frank Day, Mihir Milan Shah
  • Patent number: 11436402
    Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: September 6, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Miao Liu, Liqun Deng, Guozhi Xu
  • Patent number: 11429770
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: August 30, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dua, Amit Aggarwal, Manu Chopra, Hemant Gupta, Amit Sharma, Abhishek Raheja
  • Patent number: 11393520
    Abstract: The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinod Kumar, Prakash Kumar Lenka
  • Patent number: 11386322
    Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 12, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Weibin Ding, Jie Chen, Chao Luo, Xin-Lei Zhang
  • Patent number: 11379646
    Abstract: The present disclosure relates to electronic circuit design, and more specifically, to determining the computational requirements of fully synthesizing a printed circuit board and/or package. Embodiments may include receiving, using a processor, one or more PCB electronic design files and determining whether the PCB electronic design files include data required for a synthesis engine. If any data is missing, the method may include inferring one or more parameters using an inference engine and providing the one or more parameters to the synthesis engine, wherein the synthesis engine includes at least one of a placement, via assignment, routing, and metal pouring processes. The method may also include collecting process data from the placement, via assignment, routing, and metal pouring processes and training a machine learning system using the process data.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jorge Alejandro Gonzalez, Shang Li, Luke Roberto
  • Patent number: 11381208
    Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path. Embodiments also include at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Clarence Kar Lun Tam, Guillaume Fortin
  • Patent number: 11379753
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tulio Paschoalin Leao, Gabriel Guedes de Azevedo Barbosa, Artur Melo Mota Costa, Alberto Manuel Arias Drake, Guilherme Seminotti Braga, Rodrigo Fonseca Rocha Soares, Rogério de Souza Moraes, Paula Selegato Mathias, Tales Bontempo Cunha