Abstract: An encryption system employing a one-time key-pad uses a shared secret number and a one-way hash function with which both the originator and recipient of a message generate successive segments of a key-pad to encrypt and decrypt the message respectively. In one arrangement each key-pad segment is generated by applying the hash function to a combination of the secret number and the previous key-pad segment. In the other embodiment of the invention, each key-pad section is generated by applying the one-way hash function to a combination of the secret number and a corresponding segment of the ciphertext version of the message.

Abstract: A system for stripping frames transmitted by a station on a token ring network is disclosed. During operation of the system, the station receives a grant of permission to transmit onto the network. In an example embodiment, the grant of permission is a token. After receipt of the grant of permission to transmit, the station transmits one or more information frames onto the network. Upon transmission of the information frames, the station stops forwarding frames received from the network, thus removing received frames from the network. Removing received frames from the network is referred to as `stripping`. Following transmission of the information frames, the station transmits an end strip delimiter frame onto the network. Upon receipt of the end strip delimiter frame, the station terminates stripping. In an example embodiment, the system is used in a bridge station, the bridge station connecting a first network with a second network.

Abstract: A signature system, such as an El Gamal or DSS system, involving the use of a long-term secret number and a per-message secret number generates the per-message secret number without the use of a random number generator or non-volatile storage. The per-message secret number is generated by applying a one-way hash function to a combination of the long-term secret number and the message itself.

Abstract: Two devices HR and FR are coupled to a bus with a common memory via a port controller. Device HR requires a high (or maximum) average rate of access, device FR requires a fast response (minimum latency) in establishing access. Request signals HRQ, FRQ from the devices are latched by latches 20 and 21, passed as HRX, FRX through an arbitration or resolver circuit 22 as HRY, FRY to a sequence control unit 23 to initiate an access cycle. Cycle timing is determined by a delay line timebase circuit 24, which responds to a single change of level of a signal DLY (in either direction). Latch 21, when set, generates an request pending signal FRRP which is fed to the HR device to cause it to increase its cycle length so that the FR access cycle will finish before the next HR access cycle is initiated.