Abstract: A photodiode of a CMOS image sensor and a method for manufacturing the same are provided, in which ions implanted in the vicinity of a device isolation film are prevented from being diffused into a photodiode region to reduce a dark current. The photodiode of a CMOS image sensor includes a heavily doped P-type semiconductor substrate, a lightly doped P-type epitaxial layer formed on the semiconductor substrate, a gate electrode formed on the epitaxial layer, a device isolation film and an N-type photodiode region formed in the epitaxial layer, an insulating film formed on the epitaxial layer to open a portion between the device isolation film and the photodiode region, and a heavily doped P-type diffusion region formed in the epitaxial layer between the device isolation film and the photodiode region.
Abstract: Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate on either side of the gate electrode; a PMD (poly-metal dielectric) liner nitride layer having a non-stoichiometric structure formed on the gate electrode, the source region, and the drain region; and an interlayer insulating layer formed on the PMD liner nitride layer.
Abstract: A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first plug by sequentially implanting first and second ions in the first epitaxial layer; forming a second photodiode in the first epitaxial layer; forming a second epitaxial layer in the first epitaxial layer; forming an isolation area in the second epitaxial layer; and forming a third photodiode and a second plug in the second epitaxial layer.
Abstract: Provided is an image sensor including an overcoating layer and at least two micro lenses formed on the overcoating layer. The image sensor is characterized in that the overcoating layer positioned below a clearance between the micro lenses is etched such that curved surfaces of the micro lenses extend to the etched overcoating layer, and a contamination in the bonding pad can be prevented.
Abstract: A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.
Abstract: A color filter of an image sensor, an image sensor and a method for manufacturing the image sensor are disclosed, wherein shapes of respective unit color cells closely form various color patterns, such as a red color pattern, a green color pattern and a blue color pattern, within each unit color cell in a stripe type, and various colors such as red, green and blue required for image generation are produced, without interdependence of the respective unit color cells, are normally realized to induce a finished color filter array to smoothly express more colors, so that the resolution of a generated image in an optimal state is achieved.
Abstract: There is provided a semiconductor device. The semiconductor device includes a lower electrode, a contact connected to the lower electrode to have a double trench structure, a phase change material layer accommodated in the double trench to cause a phase change between a crystalline state and an amorphous state in accordance with a change in heat transmitted by the contact, and an upper electrode connected to the phase change material layer.
Abstract: Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.
Abstract: A CMOS image sensor and fabricating method thereof enhances a light-receiving capability of an image sensor by preventing poor light-refraction characteristics at the peripheral part of a microlens. The CMOS image sensor includes at least one microlens formed by anistropic etching to have a focusing centerline, a central lens portion, and a peripheral lens portion, wherein the focusing centerline passes through the central lens portion and wherein the peripheral lens portion surrounds the central lens portion. The central lens portion has a first convex curvature based on a first radius and the peripheral lens portion has second convex curvature based on a second radius, wherein the second radius is greater than the first radius.
Abstract: The image sensor includes a semiconductor substrate, a first color filter pattern formed over the substrate, the first color filter pattern having an edge portion with a first slope, and a second color filter pattern formed next to the first color filter pattern, the second color filter pattern having an edge portion with a second slope.
Abstract: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
Abstract: A CIS and a method for manufacturing the same are provided. The CIS includes an interlayer insulation layer formed on a substrate having a photodiode and a transistor formed thereon; a plurality of color filters formed on the interlayer insulation layer and spaced a predetermined interval apart from each other; a metal sidewall formed to fill the predetermined interval between the plurality of the color filters; and a microlens formed on each of the plurality of color filters.
Abstract: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating the wafer with a photoresist layer, and patterning the photoresist layer to expose at least the edge and an upper bevel region of the wafer for etching the material layers remaining after performing the first etch.
Abstract: A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier metal layer and the second metal layer in the via hole to a predetermined depth together with selectively etching a surface of the second metal layer; forming a silicon layer on the first barrier metal and the second metal to a predetermined height; forming a second barrier metal layer on the interlayer insulating layer; forming a third metal layer on the second barrier metal layer; and forming a second barrier metal pattern and a third metal layer pattern by patterning the second barrier metal layer and the third metal layer.
Abstract: Methods for fabricating flash memory devices are disclosed. A disclosed method comprises: forming a polysilicon layer on a semiconductor substrate; injecting dopants having stepped implantation energy levels into the polysilicon layer; forming a photoresist pattern on the polysilicon layer; and etching the polysilicon layer to form a floating gate.
Abstract: A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.
Abstract: A CMOS image sensor and fabricating method thereof can enhance the quality of the image sensor by preventing unnecessary diffused reflection of light by providing an opaque filter layer next to a microlens. The CMOS image sensor includes a photodiode, an insulating interlayer, a metal line, a device protecting layer, a microlens on the device protecting layer and overlapped with the photodiode, and an opaque layer pattern on the device protecting layer next to the microlens.
Abstract: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose the lower wire. The lower wire includes a metal layer pattern and a conductive layer pattern, and the metal layer pattern has a protruding portion and the conductive layer pattern is formed on the upper part of the protruding portion of the metal layer pattern and has a hole to expose the protruding portion.
Abstract: A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide.