Patents Assigned to Dongbu Electronics Co., Ltd.
  • Patent number: 7696039
    Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 13, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Jin Jung
  • Patent number: 7698680
    Abstract: There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at least one PMOS transistor with a first power voltage; and a second power layer supplying the at least one NMOS transistor with a second power voltage. The first poly gate of the PMOS transistor is isolated from the second poly gate of the NMOS transistor.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 13, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Min Hwahn Kim
  • Patent number: 7692248
    Abstract: A semiconductor device comprising a substrate having a well region, at least one well pickup region formed on the substrate to surround the well pickup region, a first drain region formed on the substrate to be positioned on one side of the source region, and a first gate electrode formed on the substrate to be positioned between the source region and the first drain region.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: April 6, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Nam Kim
  • Patent number: 7692264
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element isolating film formed at element isolating regions of a semiconductor substrate, which is divided into active regions and the element isolating regions; a gate insulating film having openings with a designated width formed at the active regions of the semiconductor substrate; gate electrodes formed on the gate insulating film; and lightly doped drain regions and source/drain impurity regions formed in the surface of the semiconductor substrate at both sides of the gate electrodes.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: April 6, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dong Joon Lee
  • Patent number: 7692225
    Abstract: Disclosed are a CMOS image sensor and a method for manufacturing the same. The CMOS image sensor includes a photodiode area and a floating diffusion area formed on a semiconductor substrate, a transistor formed on the semiconductor substrate between the photodiode area and the floating diffusion area, an isolation layer formed below the transistor, and a channel area formed between the transistor and the isolation layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: April 6, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Keun Hyuk Lim
  • Patent number: 7687345
    Abstract: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside the trench and protruding upward from the substrate, a charge storage layer between the control gate and an inner wall of the trench, and a pair of insulating spacers formed on opposite sidewalls of the control gate with the charge storage layer therebetween. Here, the charge storage layer has an oxide-nitride-oxide (ONO) structure. Further, the depth of the trench from the surface of the substrate is greater than that of each of the source and drain diffusion regions.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Bum Lee
  • Patent number: 7687394
    Abstract: A method for forming a dielectric layer having a low dielectric constant and a method for forming copper wiring using the same are provided. In the method for forming a dielectric, an etch stop layer and a first dielectric are sequentially formed on a semiconductor substrate. Next, the first dielectric is selectively etched to form a pattern, and a second dielectric is formed thereon. Here, the second dielectric may be formed using a plasma enhanced chemical deposition method to have pores or voids therein. Then, the dielectric is planarized and a damascene copper wiring is formed. Since the dielectric includes pores or voids, it may have a very low dielectric constant, which results in an improvement in RC delay.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Patent number: 7687363
    Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Choul Joo Ko
  • Patent number: 7687306
    Abstract: A CMOS image sensor and manufacturing method thereof are disclosed. The present CMOS image sensor comprises: a semiconductor substrate including an active region having a photo diode region and a transistor region; a gate on the active region, comprising a gate insulating layer and a gate electrode thereon; a first source/drain diffusion region in the transistor region at one side of the gate electrode, including a first conductivity type dopant; a second photo diode diffusion region in the region at the other side of the gate electrode, the second diffusion region including a first conductivity type dopant; insulating sidewalls on sides of the gate electrode; and a third diffusion region over or in the second diffusion region, extending below one of the insulating sidewalls (e.g., closest to the photo diode region), and including a second conductivity type dopant.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Gyun Jeon
  • Patent number: 7688642
    Abstract: Provided are a SONGS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the erasing method, first electrons are erased by one of Hot Hole Injection (e.g., gate-to-drain Hot Hole Injection) or tunneling in a first step, and second electrons that are not erased in the first step are erased by the other of tunneling (e.g., gate-to-body tunneling) or HHI in a second step. Preferably, a time gap intervenes between the first and second steps.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung
  • Patent number: 7682925
    Abstract: The disclosure concerns a capacitor including a trench; an insulation layer; a first polysilicon layer; a first patterned dielectric layer; a second polysilicon layer patterned into a plurality of vertical bars in the trench; a second dielectric layer along surfaces of the first dielectric layer and the second patterned polysilicon layer; and a third polysilicon layer on the second dielectric layer.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7682928
    Abstract: There is provided a method of forming an isolation layer which prevents a failure from occurring depending on a difference in the area of the isolation layer during a planarization process of the isolation layer having a shallow trench isolation (STI) structure. The present invention implements a uniform isolation layer by forming a chemical mechanical polishing (CMP) stop layer on an isolation layer having a relatively large region and performing a planarization process using the CMP stop layer.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Il Kang
  • Patent number: 7683401
    Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are formed in the active region. A gate electrode is located between the contact metals in the active region. A first distance between the active region and the dummy active region, and a second distance between an edge of the contact metal and an edge of the active region are set such that a channel characteristic of the active region is improved.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Myung Jin Jung
  • Patent number: 7682965
    Abstract: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Sang Chul Kim, Han Choon Lee
  • Patent number: 7682957
    Abstract: A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched to expose the copper layer in the fuse region. An aluminum fuse is formed on the first insulating layer in the fuse region and connected to the exposed copper layer. A second insulating layer is formed on both the aluminum fuse and the first insulating layer and selectively etched together with the first insulating layer to expose the underlying copper layer in the pad region. An aluminum pad is formed on the second insulating layer in the pad region and connected to the exposed copper layer in the pad region. At least one third insulating layer is formed on both the aluminum pad and the second insulating layer and selectively etched to expose the aluminum pad only.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yeong Sil Kim
  • Patent number: 7683448
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor is provided. The CMOS image sensor can include a photodiode, a transfer transistor (Tx), a reset transistor (Rx), a drive transistor (Dx), and a select transistor (Sx). The CMOS image sensor includes a floating diffusion region between the transfer transistor (Tx) and the reset transistor (Rx). The gate of the drive transistor (Dx) is formed of polysilicon and extends to and is formed on the floating diffusion region.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Keun Hyuk Lim
  • Patent number: 7678643
    Abstract: Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the reset transistor, the drive transistor, and the select transistor are formed on an active region of the substrate with gate insulating layers interposed therebetween. A first diffusion region is formed of a second conductive type in a first region of the active region, where the first region does not include a floating diffusion region between the transfer transistor and the reset transistor and the photodiode region. A second diffusion region is formed of the second conductive type in the floating diffusion region at a concentration lower than that of the second conductive type first diffusion region.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: March 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Gyun Jeon
  • Patent number: 7679126
    Abstract: A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the active region, a pair of wordlines over the active region and partially overlapping the floating gates, respectively, and a gate insulation film between each wordline and the active region. The method may prevent or reduce the incidence of conductive stringers on the active region between the floating gates, to thereby improve reliability of the memory devices and avoid the active region resistance from being increased due to the stringer.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: March 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung
  • Patent number: 7678604
    Abstract: Disclosed is a CMOS image sensor and a method for manufacturing a CMOS image sensor. The method includes: (a) forming a resist film on a semiconductor substrate comprising a light sensing part, a protecting layer over the light sensing part, and an exposed bonding pad; (b) forming a color filter array on the thin resist film; (c) forming a plurality of microlenses over the color filter array; and (d) etching the resultant structure until the bonding pad is exposed.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: March 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Sik Kim
  • Patent number: 7678602
    Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The method includes: preparing a semiconductor substrate in which a device isolation region and an active region are defined; forming a gate pattern including a gate oxide layer and a gate electrode on the semiconductor substrate; implanting n-type impurity ions in a predetermined part of the active region of the semiconductor substrate to form a photodiode region; forming a spacer at a sidewall of the gate pattern; forming a p-type impurity region at a surface of the photodiode region; forming an epitaxial layer on the semiconductor substrate and the gate pattern except for on the device isolation region and the spacers by performing a selective epitaxial growth; and implanting n+ type ions in a transistor region of the semiconductor substrate below the epitaxial layer to form a source/drain region.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Eun Lee