Abstract: A semiconductor device having a variable capacitance capacitor and a method of manufacturing the same are disclosed. An example semiconductor device includes a capacitor having a bottom electrode, a dielectric layer and an upper electrode, formed on a semiconductor substrate. The example semiconductor also includes a first insulating layer formed on the semiconductor substrate to cover the capacitor, a plurality of first contact plugs formed in a plurality of first via holes of the first insulating layer, each of which is electrically connected to either the bottom electrode or the upper electrode, a first metal wiring formed on the first insulating layer and connected to the bottom electrode through the first contact plug, a second contact plug formed on the first insulating layer and connected to the upper electrode through the first contact plug, and a second insulating layer formed on the first insulating layer to cover the first metal wiring and the second contact plug.

Abstract: The present invention provides a flash memory device and a method of forming the same. The method includes: forming an isolation layer and a plurality of gate lines on a semiconductor substrate; forming a source/drain region by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask; forming a side oxide layer on sidewalls and surfaces of the gate lines; forming a side nitride layer on the side oxide layer; forming an insulation layer on the semiconductor substrate and the side nitride layer; forming a photosensitive layer pattern on the insulation layer; exposing the source region between the gate lines by etching the insulation layer using the photosensitive layer pattern as a mask; forming a polysilicon layer on the exposed source region and the insulation layer; and forming a source line by etching the polysilicon layer.

Abstract: A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench formed in a device separation area of a semiconductor substrate; a thermal oxidation layer formed in a part of the trench; an oxidation silicon layer formed on the thermal oxidation layer; and an oxidation isolation layer formed on the oxidation silicon layer and filling the trench.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.

Abstract: The present invention provides a method of forming a diffusion barrier layer comprising a TaSiN layer. The method includes depositing a TaN layer into a via hole which penetrates an insulation layer exposing a first metal line layer, and transforming the TaN layer into a TaSiN layer using a radio frequency (RF) power and a (remote) plasma using SiH4 gas. Transforming the TaN layer into a TaSiN layer may include: loading a structure including the TaN layer into a plasma reaction chamber; injecting SiH4 gas into the plasma reaction chamber; and forming the TaSiN layer by reacting Si— or Si atom-containing species with the TaN layer.

Abstract: A method for forming a dual interlayer dielectric layer, which is capable of preventing an interlayer delamination phenomenon generated between an etch stop layer and an interlayer dielectric layer is provided. An interlayer dielectric layer of a dual structure is formed such that a first interlayer dielectric layer and a second interlayer dielectric layer are sequentially stacked on the etch stop layer. The etch stop layer is formed on a substrate, the substrate having a source/drain region and a gate formed therein. The dual interlayer dielectric layer is selectively etched, and a conductive material is deposited thereon, thereby forming a contact. The O3-TEOS layer and the PE-TEOS layer used as the first interlayer dielectric layer can relieve a compressive stress and improve adhesion force, respectively, thereby preventing the interlayer delamination phenomenon.

Abstract: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties of a capacitor of the MOS varactor using the calculated values of the coefficients. According to the method, the MOS varactor model equation can be expressed by Cgate=[Cigate×Area+Cpgate×Perimeter]×N, wherein, Cgate denotes gate capacitance for voltage applied to the gate, Cigate denotes intrinsic gate capacitance, Cpgate denotes perimeter gate capacitance, and N denotes the number of gate fingers. The MOS varactor model equation can be applicable to various sized capacitors, so that it is possible to estimate a gate capacitance for voltage applied to a gate, considering the differences due to the surface shapes of a device.

Abstract: A method of fabricating a CMOS image sensor is provided, in which a trapezoidal microlens pattern profile is formed to facilitate reflowing the microlens pattern and by which a curvature of the microlens may be enhanced to raise its light-condensing efficiency. The method includes forming a plurality of photodiodes on a semiconductor substrate; forming an insulating interlayer on the semiconductor substrate including the photodiodes; forming a protective layer on the insulating interlayer; forming a plurality of color filters corresponding to the photodiodes; forming a top coating layer on the color filters; forming a microlens pattern on the top coating layer; and forming a plurality of microlenses by reflowing the microlens pattern.

Abstract: Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method thereof. In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively patterned to form a plurality of photoresist patterns. A surface of each photoresist is hardened. The hardened photoresist patterns are reflowed to form microlenses.

Abstract: A semiconductor device includes an inter-metal dielectric (IMD) formed on a substrate and having at least one via hole, a via hole formed by filling the via hole with a first metal, a reductant layer formed on the via plug and the inter-metal dielectric to a predetermined thickness, and a metal line layer formed by depositing a second metal on the reductant layer.

Abstract: Shorting of a copper line with an adjacent line in a semiconductor device during chemical mechanical polishing may be prevented and thus reliability of the semiconductor device may be improved, when the semiconductor device includes a substrate, an interlayer insulating layer formed on the substrate and having a dual trench, and a copper line formed to fill the dual trench, wherein the dual trench includes a first trench inclined at a first angle with respect to the substrate, and a second trench connected to the first trench and inclined at a second angle that is smaller than the first angle with respect to the substrate.

Abstract: Methods and devices for detecting photoresist coating failures are disclosed. A disclosed method to detect a photoresist coating failure on a semiconductor wafer comprises: loading a photoresist coated wafer on a notch position check block; rotating the coated wafer; detecting the position of a notch in the wafer; blowing air toward the surface of the wafer with at least one air nozzle located over the rotating wafer; detecting an amount of the air blown from the at least one air nozzle; and generating a coating failure signal if a variation in the amount of air blown from the at least one air nozzle is indicative of a photoresist coating failure.

Abstract: A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.

Abstract: A test pattern for analyzing a delay characteristic of an interconnection line and a method of analyzing a delay characteristic of an interconnection line using the test pattern are provided. The test pattern for analyzing a delay characteristic of an interconnection line includes: a first metal line formed as a snake shaped structure having a plurality of concave-convex sections each having the same width; a second metal line having a comb shape formed on the same layer as the first metal line such that a plurality of teeth portions of the second metal line are respectively formed between the concave-convex sections at one side of the first metal line; and a third metal line having a comb shape formed on the same layer as the first metal line such that a plurality of teeth portions of the third metal line are respectively formed between the concave-convex sections at the other side of the first metal line.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a polysilicon layer on a semiconductor substrate, forming an anti-reflection coating on the polysilicon layer, forming a photoresist (PR) layer pattern on the anti-reflection coating, etching the anti-reflection coating using the PR layer pattern as a mask in capacitive coupled plasma (CCP) equipment using CF4, Ar, and O2, so as to cause a reaction by-product generated by etching the anti-reflect coating to be deposited on sidewalls of the PR layer pattern, thereby forming spacers, and etching the polysilicon layer using the PR layer pattern and the spacers as a mask.

Abstract: Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Abstract: Disclosed are a method for forming a metal interconnection and a semiconductor device including the metal interconnection. The method includes the steps of forming a slope by etching a corner of a contact hole, which exposes a predetermined pattern formed on a substrate, forming a barrier metal layer on an interlayer dielectric layer, plasma-treating the barrier metal layer with hydrogen and nitrogen gases for about 27 to 37 seconds, heat-treating the substrate in a nitrogen atmosphere, forming a tungsten layer on the barrier metal layer through a two-step nucleation process and bulk deposition process, and performing a chemical mechanical polishing process on the tungsten layer until the interlayer dielectric layer is exposed. The method and the semiconductor device prevent defects of the metal interconnection, such as a volcano defect caused by fluorine penetration.

Abstract: A method of fabricating a semiconductor device consistent with the present invention, the method comprising: forming an insulation film on a substrate; forming a mono-atomic layer of barrier ions at the insulation film; forming a gate insulation film in which the barrier ions are stabilized by an annealing process; forming a gate electrode on the gate insulation film; forming a spacer at a side surface of the gate electrode; and forming source/drain impurity regions at a side surface of the gate electrode.

Abstract: Disclosed are: (i) a method for forming an intermetal dielectric layer between metal wirings using a low-k dielectric material, and (ii) a semiconductor device with an intermetal dielectric layer comprising a low-k dielectric material. The method comprises the steps of: (a) forming a metal layer on a semiconductor substrate; (b) forming a plurality of metal wiring patterns by etching the metal layer selectively; (c) forming a first dielectric layer on the substrate and the plurality of metal wiring patterns; (d) forming a low-k dielectric layer on the first dielectric layer, the low-k dielectric layer having a lower dielectric constant than the first dielectric layer; and (e) forming a second dielectric layer on the low-k dielectric layer.

Abstract: A method for manufacturing a CMOS image sensor that independently forms a poly routing line connected to a gate poly of a reset transistor is provided. In an embodiment, a semiconductor substrate is prepared defining a device isolation region and an active region. Subsequently, a plurality of gate polys are formed on a predetermined portion of the active region. A photodiode is formed in a portion of the semiconductor substrate located at one side of one of the plurality of gate polys. After an oxide layer is deposited on the semiconductor substrate including the gate polys, the oxide layer is selectively removed to form oxide layer patterns for exposing a portion of the plurality of gate polys. After a polysilicon layer is deposited on the oxide layer pattern, the polysilicon layer is selectively removed to form a routing line connected to the portion of the plurality of gate polys.