Abstract: Organizations are disclosed for driving bit lines of a two-line 21/2D coincident current magnetic core memory in which a bit line not used for reading a bit out of a core is placed physically in parallel with the bit line driven by half select current to approximate in the unused line the capacitive and inductive coupling of the driven line with the word drive line. That coupling produces in the unused line the same noise (crosstalk) produced in the driven bit line by the word drive pulse. The crosstalk signal in the unused line is subtracted from the signal in the driven bit line before amplification and detection. The unused line may be a separate dummy line, or simply another bit line not being used for the bit being read out. In the case of paired bit lines used for common mode rejection of the bit drive signal, a second pair of unused bit lines is arranged in parallel for crosstalk cancellation.

Abstract: In a large scale addressable memory which is addressed with an applied block and word address, an auxiliary memory stores word addresses of defective locations within each block of the main memory. Such defective location addresses are supplied by the auxiliary memory in response to the applied block address. A set of comparators compare the applied word address and the defective location word addresses and signal any match. The auxiliary memory also provides a substitute location address for each stored defective location address. When a match is found by a comparator, the corresponding substitute location address is provided to the main memory to access a substitute memory location, which is known to be good.

Abstract: An electronically programmable oscillator has a plurality of digitally incremented selectable frequency signal outputs, providing a wide range of incrementally distinguishable, selectable frequencies having defined pulse widths. Incremental frequency selection is made through delay lines and bypassable interpolating delay lines connected in series. Selectable bypassable delay loops can be inserted into the oscillator signal path by manually controlled electronic, programmable selections. The width and shape of the pulse is regulated at several stages of the circuit, using solid state electronic components.

Abstract: A sense line termination circuit is provided intercoupled between a sense line of a plurality of static memory cells and a supply bus of high pull-up voltage to provide fast access to the memory cells with limited medium power dissipation. The termination circuit functions to pull up the sense line toward a predetermined intermediate high voltage value (which is about one threshold voltage Vt below the high pull-up voltage) when no memory cell has a low voltage memory node coupled to the sense line. The sense line termination circuit limits the voltage excursion of the sense lines and also permits the sense line to be pulled down with predetermined current limitation to a low voltage value when the sense line is coupled to a low voltage memory node.

Abstract: An improved driving circuit is provided especially for use in an integrated circuit semiconductor memory which operates on low power supply voltage, such as 5 volts, the drive circuit employing field effect transistors coupled with bootstrap capacitor devices and responsive to an input pulse for supplying, at its output terminal, a pulse having a peak voltage potential substantially equal to the power supply voltage value despite the inherent threshold voltage drops of the field effect transistors utilized. In the drive circuit, in response to an input pulse, the reference voltage for charged capacitor devices is switched between a first level and a raised second, higher level to place the capacitor devices in series with each other and the raised reference voltage to overdrive an output switch device so as to connect substantially its full power supply voltage to its output terminal during a corresponding output pulse.

Abstract: A read and write drive system is disclosed for a 21/2D coincident current magnetic core memory of the type in which for each word bit, bit lines threaded through the magnetic cores are arranged in a matrix of M groups, each of N bit lines. The drive system includes for the bit line matrix of each word bit a separate set of M write drive switches, and for n matrices of n different word bits, wherein n .gtoreq. 2, M read sink switches, N read drive switches and N write sink switches. These switches are used to apply 1/2 drive current through selected bit lines, during the read operation, to read out the n word bits of a selected word and to apply 1/2 drive current to independently store either a binary 1 or a binary 0 in each of the n word bits. The total number of switches, required for n word bits, is M(n+1) + 2N switches.

Abstract: A wedge lock unit is disclosed for clamping a subsystem chassis with two outwardly extending spaced apart flanges to a system main frame, from which a single flange or tab extends outwardly. The wedge lock unit includes a stationary member which is fixedly attached to one of the flanges of the subsystem chassis. The stationary member has two opposite wedged or sloping sides along which two movable wedging members with mating sloping sides rest. A drive mechanism, in the form of a rotatable screw, is used to apply a force, resulting in a clamping force, which urges the movable wedging members toward the tab of the main frame, which is inserted between the wedge lock unit and the other flange of the subsystem chassis, until the tab becomes clamped between the movable wedging members of the wedge lock unit and the other flange of the subsystem chassis. Spring means are provided which produce a reaction force on the movable wedging members. The reaction force direction is opposite the clamping force direction.

Abstract: Start-up power control of a full wave rectifier supply to a DC permanent magnet motor is provided by an SCR full wave rectifier bridge and a start-up control circuit for the SCR's comprising an independent rectifier for charging up a capacitor through a high impedance path to produce a start-up ramp voltage, a UJT relaxation oscillator powered by the independent rectifier bridge to trigger the SCR's through a transformer, and a series transistor control circuit for the UJT responsive to the ramp voltage to advance the firing angle of th UJT and thereby advance the firing angle of the SCR's as the ramp voltage increases fron 0 to a maximum.

Abstract: A utility billing transactor is disclosed for entering a new meter reading, computing the amount of utility service delivered as the difference between a previous meter reading and the new meter reading, computing the amount to be paid, and printing a bill showing the new meter reading and the amount due. A card, which has the customer's identification (ID) number, previous meter reading and billing rate code entered on it, is inserted into the transactor to initiate automatic sequencing of steps to: read the ID number, call for keyboard entry of a new meter reading, read the previous meter reading, compute the difference between the meter reading, compute the amount due as the product of a rate or schedule of rates determined from the billing rate code (either directly or through a table stored in a read-only memory) and printing the bill. The entire transaction, including data read from the card and data computed is recorded in nonvolatile memory and immediately checked for recording error.