Abstract: A semiconductor memory device having an error correcting function, includes a memory array having a data area and a check code area, an operation circuit including an encode circuit coupled to the data area and the check code area, and a decode circuit coupled to the check code area, and a control circuit including a first register coupled to the operation circuit.

Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

Abstract: A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a second internal voltage generator generating a second internal voltage in response to the external power supply voltage, the second internal voltage is larger in absolute value than the first internal voltage, and a preset signal generating circuit responding to a power-on of the external power supply voltage to the semiconductor apparatus and generating first and second preset signals which bring the first and second internal voltage generators into respective initial states, generation of the second preset signal is stopped after stopping generation of the first preset signal, in which the first internal voltage generator is released from its initial state in response to the stopping the generation of the first preset signal to be allowed to generate the first internal voltage, the second internal voltage generator is released from its initial state in

Abstract: The semiconductor memory device includes a control circuit that performs control of reading data from and writing data into each memory cell. The control circuit includes a flip-flop circuit that stores the data read from the memory cell and stores the data to be written into the memory cell and a dynamic type holding circuit connected to the flip-flop circuit through a switch. The dynamic-type holding circuit temporarily stores the data read from the memory cell. When the data read from the memory cell and then held in the holding circuit is different from the data in the flip-flop circuit to be written, supplied from an outside at a time of writing into the memory cell, control is performed so that the data in the flip-flop circuit is written into the memory cell.

Abstract: A band-gap reference voltage source circuit is constituted of a diode-pair circuit connected to a reference voltage output terminal, a first differential amplifier including a first transistor and a first operational amplifier, and a second differential amplifier including a second transistor and a second operational amplifier. The second differential amplifier operates based on a bias voltage, which is lower than a predetermined voltage, so as to forcedly pull up the level of the reference voltage output terminal via the second transistor before the first differential amplifier starts to pull up the level of the reference voltage output terminal up to the predetermined voltage via the first transistor.

Abstract: A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.

Abstract: A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.

Abstract: A conductive film is formed to extend from a bottom and a sidewall of a recess formed in an interlayer insulating film onto a top surface of the interlayer insulating film. Dry etching of the conductive film is performed such that a portion of the conductive film remains on the bottom and sidewall of the recess. The dry etching is also performed such that a deposition film is formed on a top portion of the recess.

Abstract: A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: A semiconductor device comprises an internal voltage generator circuit which includes a first transistor having a first and a second main electrode and a control electrode, a control circuit controlling a voltage between the second main electrode and the control electrode of the first transistor such that a voltage at the first main electrode of the first transistor remains at a predetermined voltage, and a second transistor having a first and a second main electrode and a control electrode. A voltage between the second main electrode and the control electrode of the first transistor is applied between the second main electrode and the control electrode of the second transistor.

Abstract: A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.

Abstract: A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

Abstract: A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect and a space thereon within the first interconnect trench, and a second interconnect and a space thereon within the second interconnect trench; forming a first trench larger in width from the first interconnect trench and a second trench larger in width from the second interconnect trench, by conducting isotropic-etching; and forming a first insulating film within the first trench and a second insulating film within the second trench by filling an insulating material in the first trench and the second trench.

Abstract: There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the drain region; a second inter-layer insulation film covering the first contact plug; a groove extending in the second inter-layer insulation film in a same direction as an extending direction of the gate electrode and exposing a top surface of the first contact plug at a bottom thereof; a second contact plug connected to the first contact plug and formed in the groove; and a wiring pattern extending on the second inter-layer insulation film so as to traverse the groove and integrated with the second contact plug.

Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

Abstract: To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, and a clock generating unit that generates an internal clock signal based on the second phase determination signal. The sampling circuit includes a continuity determining circuit that fixes the second phase determination signal when a logic level of the first phase determination signal changes within a sampling cycle, an initial operation circuit that fixes the second phase determination signal at a high level until when a third phase determination signal indicates a high level, and a disabling circuit that disables an operation of the continuity determining circuit after the third phase determination signal indicates a high level.

Abstract: A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.

Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.

Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.