Patents Assigned to Fairchild Camera and Instrument Corp.
  • Patent number: 4476365
    Abstract: A method and apparatus is disclosed for forming a ball at the end of bonding wire or lead wire held in a capillary wire holding and bonding tool for ball bonding of the lead wire to an integrated circuit chip. The method of ball formation is of the type in which the end of the bonding wire is enclosed in a shroud or shield and the shield and the end of the bonding wire are flooded with an inert cover gas. Ball formation is accomplished by electrically discharging an arc between the bonding wire and the shroud for melting and forming the ball at the end of the wire. A passageway is provided for delivering and mixing hydrogen gas into the inert cover gas delivery line at a location upstream from the shroud sufficient for complete mixing. The rate of flow of hydrogen gas is metered and controlled for adjusting the percent by volume of hydrogen in the cover gas mixture to a desired range.
    Type: Grant
    Filed: October 8, 1982
    Date of Patent: October 9, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: John A. Kurtz, Donald E. Cousens
  • Patent number: 4476366
    Abstract: Apparatus and method are described for rapid ball formation at the end of lead wire retained in the capillary wire holding tool of a ball bonding machine. A circuit is coupled between the cover gas shroud and lead wire for establishing controlled electrical discharge between the end of the bonding wire and the shroud, for melting and forming a ball. The circuit includes a DC power supply for delivering a positive polarity to the shroud and negative polarity to the lead wire for drawing a discharge of electrons from the end of the lead wire to the shroud. A capacitor is coupled in series with the DC power supply for receiving the electrical discharge. An impedance is also coupled in series for limiting the electrical discharge current. Charging of the capacitor limits and shapes the electrical arc discharge to a controlled pulse profile of short duration for rapid ball formation. An electronic gate is also used to control pulse duration.
    Type: Grant
    Filed: February 1, 1983
    Date of Patent: October 9, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: John A. Kurtz, Donald E. Cousens, Mark D. Dufour
  • Patent number: 4465995
    Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.
    Type: Grant
    Filed: April 1, 1982
    Date of Patent: August 14, 1984
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: Edwin A. Sloane
  • Patent number: 4463270
    Abstract: A circuit for detecting a difference in the relative magnitudes of two voltages includes a current sensing circuit connected between the first voltage and ground to thereby cause a first current to flow in the current sensing circuit, an amplifier connected between the second voltage and ground and connected to the current sensing circuit to thereby cause a second current to flow, the second current being equal to the first current when the first voltage is equal to the second voltage, and a variable impedance inverter connected to the first voltage and connected to the amplifier, the variable impedance being controlled by the first voltage, the output of the inverter thereby being related to the difference between the first voltage and the second voltage. The invention is particularly useful for controlling a battery backup power supply in a microprocessor having a volatile memory and for creating precision delay circuits.
    Type: Grant
    Filed: July 24, 1980
    Date of Patent: July 31, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: James S. Gordon
  • Patent number: 4449065
    Abstract: A simple six-transistor input buffer for generating and applying binary function test signals to associated circuitry in an integrated circuit package. The buffer recognizes three different voltage levels of an input signal that is applied to a single input test pin and generates three corresponding binary output signals that may be used for testing various functions of the associated circuitry.
    Type: Grant
    Filed: October 2, 1981
    Date of Patent: May 15, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Thomas J. Davies, Jr.
  • Patent number: 4443493
    Abstract: In a semiconductor device, laser energy is used to selectively heat various SiO.sub.2 based materials to elevated temperatures while maintaining the active device region and electrical interconnects at relatively low temperatures, to for example, induce densification and/or flow of the SiO.sub.2 based material to round off sharp edges and stops, without damaging or affecting the active region and electrical interconnects.
    Type: Grant
    Filed: January 15, 1982
    Date of Patent: April 17, 1984
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: Michelangelo Delfino
  • Patent number: 4443295
    Abstract: A method is disclosed of etching a refractory metal layer on a semiconductor structure comprising subjecting it to a mixture of a Lewis base and an oxidizing agent. In the preferred embodiment a method is described for etching a tungsten-titanium layer on a semiconductor structure by immersing it in a mixture of triethylamine and hydrogen peroxide.
    Type: Grant
    Filed: June 13, 1983
    Date of Patent: April 17, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Kenneth J. Radigan, James M. Cleeves
  • Patent number: 4442449
    Abstract: An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type commonly used in the semiconductor industry. The resulting alloy can be oxidized, selectively removed and doped with selected impurities to provide a conductive lead pattern of a desired shape on the surface of a wafer.
    Type: Grant
    Filed: March 16, 1981
    Date of Patent: April 10, 1984
    Assignee: Fairchild Camera and Instrument Corp.
    Inventors: William I. Lehrer, Bruce E. Deal
  • Patent number: 4423491
    Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.
    Type: Grant
    Filed: November 23, 1981
    Date of Patent: December 27, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Andrew C. Tickle
  • Patent number: 4419656
    Abstract: A method and apparatus is described for dynamically testing the overall performance characteristics of digital-to-analog converts and analog-to digital converters which involve excitation of the converters by an orthogonal function signal. Specifically the method comprises dynamically exercising a converter with an analog or digital signal pattern characterized by the sum of a set of mutually orthogonal functions, the sum having substantially uniform amplitude distribution among allowable states (maximum entropy), and simultaneously examining the output response of the converter for a plurality of basic performance parameters. The basic performance parameters typically include distortion, linearity and optimum gain. The simultaneous examination involves sorting out expected responses to simultaneously applied orthogonal signals. The method yields a relatively complete statistical description of the performance characteristics. The preferred excitation is based on the Walsh functions.
    Type: Grant
    Filed: November 7, 1980
    Date of Patent: December 6, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Edwin A. Sloane
  • Patent number: 4412283
    Abstract: A microprocessor comprising: an address data path; an arithmetic logic unit data path, said data paths being capable of simultaneous operation; an information bus; a shared bus register; a shared input multiplexing apparatus for selectively transferring address and data information from said information bus and data information from said arithmetic logic unit data path to said shared bus register; and a multiplexing apparatus for transferring information from said shared bus register to said arithmetic logic unit data path and to said information bus via said address data path whereby said shared bus register is selectively useable as a memory data register, a memory address register and a temporary or "scratch-pad" register during normal operation of the microprocessor; and further comprising; a programmable logic array containing a sequence of microinstructions and apparatus connected thereto for testing the operability of the microprocessor.
    Type: Grant
    Filed: May 30, 1980
    Date of Patent: October 25, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Yeshayahu Mor, Dan Wilnai
  • Patent number: 4398338
    Abstract: A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region.
    Type: Grant
    Filed: December 24, 1980
    Date of Patent: August 16, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: Andrew C. Tickle, Madhukar B. Vora
  • Patent number: 4396980
    Abstract: A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.
    Type: Grant
    Filed: July 11, 1980
    Date of Patent: August 2, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Hemraj K. Hingarh
  • Patent number: 4393473
    Abstract: Circuitry for presetting a bipolar random access memory includes switching transistors, responsive to an applied memory preset signal, for opening the circuit between the memory word lines and their respective current sources, for applying a positive voltage to the bottom word lines, for breaking the circuitry between bit line clamping circuits and their respective power sources, and for grounding the bit line pairs to drain all current from the bit line circuits. The preset circuitry also includes read/write control transistors coupled between each bit line and a V.sub.cc source for steering the set of the memory cells upon removal of the preset signal.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: July 12, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Roger V. Rufford
  • Patent number: 4393476
    Abstract: A discharge circuit for rapidly discharging the word lines of random access memories to thereby prevent erroneous reading from or writing into the memory during periods when the word lines are in a mid-state transition between selected and deselected voltage levels. Each discharge circuit associated with the memory word lines includes a transistor that is conductive only when a full select voltage level is applied to the word line and which controls conduction of a second multi-collector transistor coupled between top and bottom lines of a word line pair and a current source to discharge the word line pair during the mid-state transition period and to thus increase the speed capabilities of the memory.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: July 12, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Warren R. Ong
  • Patent number: 4390771
    Abstract: Method and apparatus for forming a ball at the end of bonding wire or lead wire in a capillary wire holding and bonding tool is described suitable for ball bonding of copper and aluminum lead wire to integrated circuit chips. A ball is formed by substantially enclosing the end of the bonding wire in a shroud or shield, flooding the shroud or shield and the end of the bonding wire with an inert gas, and generating a controlled pulse train of a preset count of electrical pulses for establishing arc discharge between the wire and the shroud or shield. The method permits precise control and metering of energy delivered by controlling the parameters of the pulses of the pulse train for melting and forming a ball of uniform quality without oxidation of the metal. Corresponding apparatus and circuitry are described which may be retrofitted into stock ball bonding machines or provide new machines.
    Type: Grant
    Filed: May 11, 1981
    Date of Patent: June 28, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: John A. Kurtz, Donald E. Cousens
  • Patent number: 4390598
    Abstract: A lead frame (20) for tape automated bonding includes individual leads (12) each having a stretch loop (40) to accommodate elongation of the loop as the lead is bonded to a substrate (28) after inner lead bonds have been formed to an integrated circuit (26). Such a lead frame allows temporary connection and testing of the circuit prior to final lead formation and packaging.
    Type: Grant
    Filed: April 5, 1982
    Date of Patent: June 28, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: William S. Phy
  • Patent number: 4388525
    Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.
    Type: Grant
    Filed: February 11, 1981
    Date of Patent: June 14, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: William S. Phy
  • Patent number: 4387145
    Abstract: A method for forming a predetermined configuration of a film material comprises the steps of forming a layer of a first material on a surface, forming a layer of a second material on the first material wherein the first material has an etch rate greater than that of the second material when the first material and the second material are exposed to a common etchant, etching portions of the second material and underlying portions of the first material to expose portions of the surface, forming a layer of film material on the exposed portions of the surface, forming a layer of film material on the exposed portions of the surface and on the remaining portions of the second material, and removing the remaining portions of the first material such that the overlying second material and the film material thereon is also removed.
    Type: Grant
    Filed: September 28, 1981
    Date of Patent: June 7, 1983
    Assignee: Fairchild Camera & Instrument Corp.
    Inventors: William I. Lehrer, John H. Vincak
  • Patent number: 4386420
    Abstract: A method and circuitry (5) for enhancing the reproducibility and reliability of circuitry for reading a memory array (10a, 10b, 10a', 10b') provides a dynamically generated reference voltage for the sensing circuitry. The invention senses the highest word line voltage and communicates a voltage derived therefrom to the sensing circuitry (26, 27, 28, 29; 26', 27', 28', 29'; 32, 33) to provide a reference voltage. A voltage clamp (62) is coupled to the circuitry for communicating the highest word line voltage (50) to prevent the reference voltge from following the word line too low during transitions. The invention is rendered compatible with the existing write circuitry associated with the memory array (10a, 10b, 10a', 10b') by the provision of disabling circuitry (65) coupled to the communicating circuitry (55, 57) and to the clamp (62).
    Type: Grant
    Filed: October 19, 1981
    Date of Patent: May 31, 1983
    Assignee: Fairchild Camera and Instrument Corp.
    Inventor: Warren R. Ong