Abstract: A regulated substrate bias voltage generating system for maintaining a minimum data retaining current through an associated MOS memory. The negative substrate bias voltage is generated by a charge pump operating under the control of a two-phased output oscillator, the operation of which is enabled and disabled by the output signals from a MOS memory over-current sensor, a MOS memory under-current sensor, and a bias voltage level sensor.

Abstract: A printed circuit board test fixture having interchangeable top plates (card personalizers). The test fixture is provided with a vacuum well having a field of probes mounted therein. The field of probes corresponds to the sum of all test points of a family of different printed circuit boards. Only a portion of all the probes are necessary to test any particular type of circuit board of the family. The top plate for each type of circuit board in the family has holes drilled completely therethrough only at locations where selected probes must pass through the top plate in order to contact the test points on the circuit board. In a preferred form, each top plate is partially drilled therethrough to form sockets at locations corresponding to the remaining probes which need not contact a particular circuit board. A hinged cover is provided for the vacuum well to allow easy removal and insertion of top plates.

Abstract: In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.

Abstract: A voltage protection circuit for controlling an input data signal on a signal-carrying line to a binary data-storage device having an input line for receiving the input data signal comprises two transistors in series having current-control electrodes coupled to an input control terminal and a third transistor having its current-control electrode coupled to the input line with one current-conducting electrode coupled to a voltage source and another current-conducting electrode coupled to current-conducting electrodes of the first two transistors.

Abstract: A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used.

Abstract: A transistor interface circuit for switching analog differential pairs in response to a flip-flop or combinational logic, both output signals of which remain either high or low during switching transitions. This circuitry prevents the differential pair from momentarily saturating or shutting off during the switching transition.

Abstract: A precision motor speed control system employing a phase locked loop in which the inertial mass of the motor, its tachometer and motor driven devices, such as fly wheels, tape transports, etc., perform the functions of the usual low pass filter and voltage control oscillator.

Abstract: A power supply circuit impresses a signal supplied by a pulse generator (28) at one frequency on an alternating current such as a standard AC signal at 115 volts RMS and 60 hertz by utilizing a single switching transistor (Q1) coupled between the pulse generator (28) and a current-directing element (14) which, in turn, is serially coupled between a source (10) of the alternating current and a load (18). The resultant bidirectional output voltage across the load (18) may be rectified and averaged to produce a substantially constant DC voltage whose level is regulatable by controlling the duty cycle of the pulse generator (28).

Abstract: A programmable microcomputer controlled alarm clock has a multi-key input keyboard for setting the time of day, the month and date, and the alarm times of two or more independent alarms. Each alarm may be set to generate an alarm signal at a selected time on each day of two to six consecutive days of a seven-day period, the alarm sequence being automatically repeated each following seven-day period. In the normal operational mode, time of day is displayed until a month-and-date switch, an alarm-period or doze switch, or an alarm-enabling switch is actuated to display the respective date and alarm time. After the particular switch is actuated and the appropriate time information displayed, the clock returns to display time of day within several seconds.

Abstract: A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

Abstract: This invention relates to a structure for testing the integrity of a printed circuit board test fixture and to a method for implementing the verification of the fixture.

Abstract: A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.

Abstract: A transistor logic tristate output device with plural phase splitter transistor means coupled in parallel configuration jointly to control sinking of current by the pulldown element with only one of the plural phase splitter transistor means coupled to control sourcing of current by the pullup element. In a preferred embodiment dual phase splitter transistors define a relatively low resistance path from high potential for controlling the pulldown element and a relatively high resistance path from high potential through the enable gate restricting power consumption in the high impedance third state.

Abstract: An electronic system for testing an electronic device responsive to a data clock signal and to a serial input data signal synchronous with the data clock signal comprises an oscillator for generating oscillator pulses, a data clock signal generator responsive to oscillator pulses for generating the data clock signal, timing circuitry for counting oscillator pulses and for generating at least one input select signal indicative of the number of oscillator pulses counted, and multiplexing circuitry for receiving at least two parallel input data signals and for sequentially selecting the parallel input data signals in response to the input select signal or signals to generate the serial input data signal.

Abstract: A compact bistable semiconductor memory cell usable in static electronic information storage devices includes a field-effect transistor merged with a bipolar transistor for storing a binary information bit.

Abstract: An ignition control system typically used with an automobile engine provides tight feedback control on engine timing. An integrator produces a waveform which is typically dual-slope in response to a timing signal supplied by a sensor responsive to rotation of a distributor. A dwell-control circuit produces a dwell-control reference signal which varies with the integrator waveform voltage at low engine speed. A comparator generates an output drive-control signal when the integrator waveform voltage equals or is less than the dwell-control reference voltage. An output drive circuit produces an activation signal in response to the drive-control signal to activate an output drive circuit which then supplies an ignition signal to an ignition coil. A feedback loop between the output drive circuit and the output drive-control circuit causes the output drive circuit to stabilize at a selected state such as a specified output current level.

Abstract: A plurality of charge-coupled device shift registers or shift register elements is used to generate a plurality of packets of charge, each proportional to a different reference potential. Using a sense amplifier or comparator, each of the packets of charge is compared, either simultaneously or sequentially, with one or more packets of charge generated by the potential of an analog signal. Signals from the comparator are then supplied to an encoder or a counter to generate a digital signal representative of the analog signal. In one embodiment the plurality of different reference potentials are generated by positioning the shift registers or shift register elements at various locations along a resistance having a potential applied across it.

Abstract: Read-only memories are manufactured to include the associated microprocessor controlling program specified by, and proprietary to, the manufacturer's customers. The problem the manufacturer has of identifying each ROM and associated microprocessor with each customer is now overcome by including an assigned customer identification number in a separate small permanent register that may be read out into the data bus by an appropriate input signal. Stored program security is provided by including in the ROM test circuit a fusible link that may be opened by an appropriate signal to prevent all future readout of the customer's proprietary program.

Abstract: A process for patterning regions on a semiconductor structure comprises the steps of forming a first layer of an alloy of tungsten and titanium on the semiconductor structure, forming a conductive layer of aluminum or chemically similar material on the surface of the tungsten-titanium alloy, removing the undesired portions of the conductive layer by etching with a plasma and removing the thereby exposed portions of the tungsten-titanium alloy layer by chemical etching.

Abstract: A semiconductor memory cell comprising first and second bipolar cell transistors cross-coupled by the inverse transistor action of third and fourth bipolar transistors. Each cross-coupling transistor is formed by a single emitter diffusion in an existing common base region of one cell transistor, above a common buried collector region of the same cell transistor. The use of cross-coupling transistors eliminates the need for a direct ohmic connection to the buried layer collector, thereby simplifying layout and reducing memory cell size.