Patents Assigned to Fairchild Semiconductor Corporation
  • Patent number: 10090757
    Abstract: A Power Factor Correction (PFC) circuit includes an oscillator circuit. The oscillator circuit receives a valley detect signal indicating a zero current condition, determines a blanking time according to an operational cycle of the PFC circuit, and determines to initiate the operational cycle according to the valley detect signal and the blanking time. Determining the blanking time includes selecting one of a plurality of predetermined blanking times according to a count of operational cycles of the PFC circuit. The PFC circuit may operate in a Boundary Conduction Mode or a Discontinuous Conduction Mode depending on whether a charge-discharge period is greater than the blanking time. The PFC circuit may determine, according to its output voltage, a first duration of a charging period, determine a delay time according to zero current times of previous operational cycles, and extend the first duration of the charging period by the delay time.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: October 2, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jintae Kim, Sangcheol Moon, Hangseok Choi
  • Publication number: 20180269302
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Salman AKRAM, Venkat ANANTHAN
  • Publication number: 20180269138
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 10065851
    Abstract: This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 4, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Janusz Bryzek
  • Patent number: 10060757
    Abstract: This document provides apparatus and methods for cancelation of quadrature error from a micro-electromechanical system (MEMS) device, such as a MEMS gyroscope. In certain examples, a quadrature correction apparatus can include a drive charge-to-voltage (C2V) converter configured to provide drive information of a proof mass of a MEMS gyroscope, a sense C2V converter configured to provide sense information of the proof mass, a phase-shift module configured to provide phase shift information of the drive information, a drive demodulator configured to receive the drive information and the phase shift information and to provide demodulated drive information, a sense demodulator configured to receive the sense information and the phase shift information and to provide demodulated sense information, and wherein the quadrature correction apparatus is configured to provide corrected sense information using the demodulated drive information and the demodulated sense information.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: August 28, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ion Opris, Hai Tao, Shungneng Lee
  • Patent number: 10054617
    Abstract: This application discusses, among other things, zero current detection. In an example, a circuit for zero current detection can include a compensating circuit and a detecting circuit. The compensating circuit can be configured to feed back a compensating voltage to the detecting circuit according to an output voltage of a DC-DC converting circuit. The detecting circuit can be configured to dynamically adjust an intentional offset voltage according to the compensating voltage, and to perform zero current detection of the DC-DC converting circuit according to the adjusted Voffset.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: August 21, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maoxu Li, Dong Li
  • Patent number: 10056753
    Abstract: This document discusses, among other things, an electro-static discharge (EDS) filtering circuit and method, a reset circuit, and an electronic device. The ESD filtering circuit comprises a first current dividing circuit and a second current dividing circuit which respectively share a current of a first power source signal and aggregate the shared currents to form a second power source signal upon filtering, wherein a voltage drop of the first current dividing circuit is constant and the second current dividing circuit is a pure resistor element circuit.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 21, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Peng Zhu, Lei Huang, Yongliang Li
  • Patent number: 10050155
    Abstract: This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: August 14, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Cenk Acar
  • Patent number: 10038385
    Abstract: In one embodiment, a power supply controller, or alternately a semiconductor device having a power supply controller, may have a circuit configured configuring the PWM circuit to form a first signal having a value formed to be representative of a peak value of a primary current through the power switch and having a duration that is representative of a time interval that a secondary current is flowing through a secondary winding wherein the peak value is the peak value during an on-time of the power switch, and configured to form a current having a value that is representative of an average value of the secondary current.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 31, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Lei Chen, Chih-Hsien Hsieh, Yue-Hong Tang
  • Patent number: 10038370
    Abstract: A capacitor input circuit for a mobile power supply includes a bulk capacitor and a switch. The switch connects the bulk capacitor to receive a rectified AC voltage from a rectifier when an AC line voltage input to the mobile power supply is lower than a threshold voltage. When the AC line voltage is greater than the threshold voltage, the switch electrically floats the bulk capacitor.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 31, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Richard Nicholson
  • Patent number: 10027235
    Abstract: A flyback converter includes a primary-side switch that controls conduction of current on a primary side of a transformer and a synchronous rectifier on a secondary side of the transformer. A synchronous rectifier driver controls the conduction of the synchronous rectifier by adaptively adjusting a turn-off threshold of the synchronous rectifier.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 17, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Hangseok Choi, Lei Chen, Cheng-Sung Chen
  • Patent number: 10027165
    Abstract: An electrical circuit for a power supply includes a primary-side controller integrated circuit (IC) that outputs a drive signal on a switch pin to control a switching operation of a switch that is coupled to a primary winding of a transformer. The primary-side controller IC places the switch pin at high impedance during a sense window and turns on the switch in response to sensing a dynamic detection signal on the switch pin during the sense window. The dynamic detection signal is induced by a secondary-side controller IC by controlling switching of a switch that is coupled to a secondary winding of the transformer when the output voltage drops below a predetermined threshold during standby or other low load conditions.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 17, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo Tao, Zhao-Jun Wang, Chih-Hsien Hsieh, Li Lin
  • Patent number: 10014695
    Abstract: In a general aspect, a battery pack can include a battery configured to supply power to a connected device and to receive re-charge power from a charger circuit. The battery pack can further include a current modulating circuit configured to modulate current of the battery between first and second supply terminals of the battery pack. The battery pack can also include a controller configured to provide voltage protection of the battery pack and charge current control of the battery using the current modulating circuit. The controller can be configured, while the battery is being charged, to compare, at the battery pack, a charge voltage setpoint of the battery pack with a desired charging voltage; modify, at the battery pack, the charge voltage setpoint to achieve the desired charging voltage; and provide the modified charge voltage setpoint from the battery pack to a connected device.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: July 3, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Philip J. Crawley
  • Patent number: 10015608
    Abstract: In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 3, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Philip Crawley, William D. Llewellyn, Majid Shushtarian, Earl D. Schreyer
  • Patent number: 10015578
    Abstract: Apparatus and methods for reducing crosstalk in personal audio equipment are provided. In an example, a method to reduce headset audio crosstalk can include applying a first signal to a first speaker channel of a headset, coupling a second speaker channel to a first input of a comparator of a crosstalk compensation circuit using a first switch of the crosstalk compensation circuit, the switch and detect circuit including the crosstalk compensation circuit, coupling a first resistor divider to a second input of the comparator using a second switch of the crosstalk compensation circuit, and adjusting a resistance setting of the first resistor divider from an initial setting using an output of the comparator.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 3, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Oscar W. Freitas
  • Publication number: 20180184221
    Abstract: This document discusses, among other things, systems and methods to reduce power use of an accessory detection device. The accessory detection device can be configured to be coupled to a mobile device having an audio jack configured to be coupled to a mobile device accessory having a send/end key. In an example, the accessory detection device can include a comparator and a switch. The comparator can be configured to receive mobile device accessory information from the mobile device accessory and to determine activation of the send/end key using the received mobile device accessory information. The switch can be configured to receive connection information indicative of mobile device accessory connection to the audio jack and to isolate a reference input of the comparator from a supply voltage using the connection information, for example, to reduce leakage current.
    Type: Application
    Filed: March 22, 2017
    Publication date: June 28, 2018
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Seth M. Prentice, Julie Lynn Stultz
  • Patent number: 10002941
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a first well region, a second well region disposed in the SiC epi-layer, a first source region disposed in the first well region, and a second source region disposed in the second well region. The device can further include a gate structure disposed on the SiC epi-layer and extending between the first source region and the second source region. The gate structure can include a hybrid gate dielectric. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 19, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Salman Akram, Venkat Ananthan
  • Patent number: 10002061
    Abstract: Systems and methods are disclosed, including a USB interface detector, a detection method, a USB connector, and an electronic device. The detection method may be applicable to the USB connector mounted in the electronic device. According to an operation mode of the electronic device, a first pin and a second pin in the USB interface can be pulled up or pulled down. After the pull up or the pull down, a voltage change at the first and second pins are detected. If the voltage changes cross a reference voltage, an instruction related to attachment or detachment with a second device can be provided.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 19, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jianli Chen, Weiming Sun, Emma Wang, Lei Huang
  • Patent number: 9991810
    Abstract: A synchronous rectifier driver pre-positions a gate of a synchronous rectifier to allow for fast turn-off. The synchronous rectifier driver turns ON the synchronous rectifier by driving the gate at a high level for a period of time that is based on a previous conduction time of the synchronous rectifier. The synchronous rectifier driver thereafter drives the gate at a lower level that is sufficient to keep the synchronous rectifier ON. The synchronous rectifier can be quickly turned OFF by further reducing the level of the drive signal at the gate of the synchronous rectifier.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 5, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Hangseok Choi, Wei-Hsuan Huang, Cheng-Sung Chen
  • Publication number: 20180145168
    Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 24, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Andrei KONSTANTINOV