Patents Assigned to Fairchild Semiconductor Corporation
  • Patent number: 9887633
    Abstract: This disclosure provides control techniques for a resonant converter. In one embodiment, a resonant converter controller includes predictive gate drive circuitry configured to generate a predictive gate drive signal indicative of a time duration from a rising edge of a first drive signal for controlling a conduction state of a first inverter switch of a resonant converter system to a synchronous rectifier (SR) current zero crossing instant of a first SR switch of the resonant converter system, wherein the first tracking signal is based on at least the first drive signal and a voltage drop across the first SR switch. The resonant converter controller may also include SR gate drive shrink circuitry configured to generate an SR gate drive turn on delay signal to increase delay of SR on times in response to detection of a decrease in load current demand of the resonant converter system.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: February 6, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Hang-Seok Choi
  • Publication number: 20180031647
    Abstract: In one general aspect, a system includes a material including a surface, and a magnetic sensor configured to sense a first component and a second component of a magnetic field. The first component of the magnetic field may be orthogonal to the second component of the magnetic field. The magnetic sensor may include a first sense element included on a first angled surface sloping in a first direction relative to the surface of the material, a second sense element included on a second angled surface sloping in the first direction, and a third angled surface sloping in a second direction different from the first direction where the third angled surface can be disposed between the first angled surface and the second angled surface and can exclude a sense element.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Phil MATHER
  • Patent number: 9882408
    Abstract: According to one aspect of the present disclosure, there is provided a battery charging system. The battery charging system includes battery charging circuitry configured to provide charging current to a battery. The battery charging system further includes feedback circuitry configured to generate a feedback signal indicative of a battery charging condition, wherein the battery charging system is configured to control the battery charging current based on, at least in part, the feedback signal. The battery charging system further includes feed forward circuitry configured to adjust the feedback signal to decrease battery charging current when a decrease in battery current draw exceeds a threshold, and wherein the feed forward circuitry is configured to decrease the battery charging current faster than the feedback circuitry.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 30, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rendon Holloway, Qinghung (Michelle) Lee, Jonathan Klein
  • Patent number: 9877104
    Abstract: An audio switch circuit includes negative feedback paths and a transistor that serves as a switching component. The negative feedback paths are turned ON to couple a source voltage and a drain voltage of the transistor to the gate of the transistor when the audio switch circuit is turned ON. The negative feedback paths reduce the slew rate of the gate-to-source voltage of the transistor, thereby slowing the turn-ON of the audio switch circuit to prevent or minimize unwanted audible noise. The negative feedback paths can be turned OFF after a period of time after the audio switch circuit is turned ON for improved total harmonic distortion.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 23, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Lei Huang, Julie Stulz, Eric Li
  • Publication number: 20180012958
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 11, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. YEDINAK, Ashok CHALLA, Dean E. PROBST, Daniel KINZER
  • Patent number: 9856132
    Abstract: One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: January 2, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Janusz Bryzek, John Gardner Bloomsburgh, Cenk Acar
  • Publication number: 20170373008
    Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 28, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
  • Publication number: 20170366044
    Abstract: An electrical circuit for a power supply includes a primary-side controller integrated circuit (IC) that outputs a drive signal on a switch pin to control a switching operation of a switch that is coupled to a primary winding of a transformer. The primary-side controller IC places the switch pin at high impedance during a sense window and turns on the switch in response to sensing a dynamic detection signal on the switch pin during the sense window. The dynamic detection signal is induced by a secondary-side controller IC by controlling switching of a switch that is coupled to a secondary winding of the transformer when the output voltage drops below a predetermined threshold during standby or other low load conditions.
    Type: Application
    Filed: May 19, 2017
    Publication date: December 21, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Zhibo TAO, Zhao-Jun WANG, Chih-Hsien HSIEH, Li LIN
  • Publication number: 20170365583
    Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 21, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Seungwon IM, Oseob JEON, JoonSeo SON, Mankyo JONG, Olaf ZSCHIESCHANG
  • Publication number: 20170350768
    Abstract: In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 7, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Kenneth P. SNOWDON, Roy YARBROUGH
  • Patent number: 9835647
    Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 5, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ion Opris, Justin Seng, Shanthi Pavan, Marwan Ashkar, Michelle Lee
  • Patent number: 9838004
    Abstract: Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 5, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Julie Lynn Stultz
  • Publication number: 20170346385
    Abstract: A switch mode power supply controller includes a switch terminal adapted to be coupled to an inductor that drives a load, high- and low-side switches a pulse width modulation (PWM) circuit, and a current monitor circuit. The PWM circuit is coupled to a feedback terminal for receiving a feedback signal, and alternatively drives the high-side switch and the low-side switch with a duty cycle set using the feedback signal to regulate an output voltage to a desired level in a work mode, and keeps both the high-side switch and the low-side switch non-conductive in a non-work mode. The current monitor circuit provides a current monitor signal representative of a current driven from the inductor to the load, wherein the current monitor circuit forms the current monitor signal by measuring an inductor current during a work mode, and by emulating the inductor current during a non-work mode.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 30, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Enzhu LIANG, Kaiwei YAO, Ming GU
  • Publication number: 20170346328
    Abstract: In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 30, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: James A. Meacham, II, Karttikeya Shah
  • Publication number: 20170345889
    Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.
    Type: Application
    Filed: August 15, 2017
    Publication date: November 30, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Andrei KONSTANTINOV
  • Publication number: 20170338807
    Abstract: A ramp generator includes a current generator, a current mirror, and a first capacitor. The current generator has an input for receiving a clock signal, and an output for providing a current proportional to a frequency of the clock signal using a first transistor having first and second current electrodes and a control electrode, an amplifier that establishes a reference voltage on the second current electrode of the first transistor, and a variable resistor coupled between the second current electrode of the second transistor and ground whose resistance is set according to the frequency of the clock signal. The current mirror has an input coupled to the first terminal of the first transistor, and a second terminal. The first capacitor has a first terminal coupled to the output of the current mirror and providing a ramp signal, and a second terminal coupled to the first power supply voltage terminal.
    Type: Application
    Filed: May 2, 2017
    Publication date: November 23, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Hua ZHU, Kaiwei YAO
  • Patent number: 9825548
    Abstract: A switching converter includes a synchronous rectifier and a synchronous rectifier driver that controls conduction of the synchronous rectifier. The synchronous rectifier driver turns OFF the synchronous rectifier in response to a turn-off trigger. The synchronous rectifier driver prevents the turn-off trigger from turning OFF the synchronous rectifier during a turn-off trigger blanking time that is adaptively set based on a conduction time of the synchronous rectifier.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 21, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hangseok Choi, Lei Chen, Cheng-Sung Chen
  • Patent number: 9812956
    Abstract: A power supply system has a power switch circuit that switches an input voltage to generate a switched input voltage, an output circuit that generates an output voltage from the switched input voltage, and a pulse width modulation (PWM) controller that generates a PWM signal to control the power switch circuit. The PWM controller turns OFF the PWM signal based on a ramp signal that emulates a current of an output inductor and a feedback signal that indicates an error between the output voltage and a reference voltage.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 7, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Weihong Qiu, Shangyang Xiao
  • Patent number: 9812440
    Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 7, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Yongliang Li
  • Patent number: 9812976
    Abstract: A power supply includes a control transistor that controls a primary winding of a transformer to induce current on a secondary winding of the transformer to generate an output voltage. A pulse width modulation (PWM) controller integrated circuit (IC) chip drives the control transistor through a gate pin. The PWM controller IC chip has a feedback pin that receives a feedback signal indicative of the output voltage. A high voltage (HV) startup transistor is controlled through the feedback pin. The HV startup transistor turns ON during startup to generate a supply voltage from current received from the input voltage of the power supply. The HV startup transistor turns OFF when the supply voltage reaches a startup voltage level that is sufficient to start the switching operation of the control transistor and thereby receive operating current from an auxiliary winding of the transformer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: November 7, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Hangseok Choi