Abstract: A voltage regulator circuit is provided, which includes a main regulator and at least one auxiliary regulator. The main regulator provides an output voltage and regulates the output voltage according to the output voltage and a reference voltage. Each auxiliary regulator is coupled to the main regulator. Each auxiliary regulator also provides the output voltage and regulates the output voltage according to the output voltage and the reference voltage. Each of the main regulator and the at least one auxiliary regulator provides a branch current of the same magnitude. An output current of the voltage regulator circuit includes the branch currents provided by the main regulator and the at least one auxiliary regulator.

Abstract: A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector.

Abstract: A voltage regulator apparatus and an associated method are provided, where the voltage regulator apparatus includes: a voltage regulator module for regulating an input voltage according to a bandgap reference voltage to generate an output voltage; and a plurality of sensing modules. Ina situation where the output voltage abruptly decreases, a sensing module reduces, based on a variation amount of the output voltage, a decrement of the output voltage. In a situation where the output voltage abruptly increases, another sensing module reduces, based on another variation amount of the output voltage, an increment of the output voltage. In addition, yet another sensing module senses variation of the output voltage, converts the variation of the output voltage into a current signal, and applies the current signal to a control terminal within the voltage regulator module to indirectly control the output voltage.

Abstract: A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB host, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode.

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract: A voltage regulator circuit is provided, which includes a main regulator and at least one auxiliary regulator. The main regulator provides an output voltage and regulates the output voltage according to the output voltage and a reference voltage. Each auxiliary regulator is coupled to the main regulator. Each auxiliary regulator also provides the output voltage and regulates the output voltage according to the output voltage and the reference voltage. Each of the main regulator and the at least one auxiliary regulator provides a branch current of the same magnitude. An output current of the voltage regulator circuit includes the branch currents provided by the main regulator and the at least one auxiliary regulator.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.

Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.

Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.

Abstract: An image sensing apparatus, a color-correction matrix correcting method and a look-up table establishing method are provided. The image sensing apparatus calculates a block statistics value corresponding to a block of pixels in an image sensor array. Based on a look-up table, the image sensing apparatus determines a covariance value corresponding to a current gain value. According to the covariance value and the block statistics value, the image sensing apparatus corrects a color-correction matrix corresponding to the block of pixels. The image sensing apparatus can use an amended color-correction matrix to correct the color of the pixel, so as to reduce chroma noise or other noise.

Abstract: A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.

Abstract: A motion detection circuit and a motion detection method are provided. The motion detection circuit includes a motion vector (MV) filtering unit and a MV decision unit. According to a relationship between a MV of a current macro-block (MB) and MVs of spatial neighboring MBs, or according to a relationship between the MV of the current MB and the MV of temporal neighboring MB, the MV filtering unit determines whether to filter the MV of the current MB for obtaining a first filtered information of the current MB. The MV decision unit receives the first filtered information, and determines whether the current MB is a motion MB according to the first filtered information.

Abstract: An integrated circuit (IC) is provided. The IC includes a chip/die and a package. The chip/die includes a first bonding pad, a second bonding pad, a core circuit and a resistance unit. The first bonding pad is coupled to a signal path of the core circuit. The two ends of the resistance unit are respectively coupled to the first bonding pad and the second bonding pad. The package includes a pin and a low-pass circuit. The pin is electrically connected to the first bonding pad. The low-pass circuit is electrically connected to the second bonding pad.

Abstract: An image sensing apparatus, a color-correction matrix correcting method and a look-up table establishing method are provided. The image sensing apparatus calculates a block statistics value corresponding to a block of pixels in an image sensor array. Based on a look-up table, the image sensing apparatus determines a covariance value corresponding to a current gain value. According to the covariance value and the block statistics value, the image sensing apparatus corrects a color-correction matrix corresponding to the block of pixels. The image sensing apparatus can use an amended color-correction matrix to correct the color of the pixel, so as to reduce chroma noise or other noise.

Abstract: In a method for estimating image noise, plural sample blocks of an image are determined; a mean of at least one color component of each of the sample blocks and a standard deviation of at least one color component of each of the sample blocks are calculated; the sample blocks are distributed into plural segments according to the means of the sample blocks; a weighted average of the standard deviations of all of the sample blocks of each of the segments is calculated according to at least one threshold value that is determined according to the minimum standard deviation among the standard deviations of all of the sample blocks of the segment. The weighted average may be applied to noise reduction, edge detection, or motion detection of the image.

Abstract: A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: A voltage regulator calibration circuit including a voltage regulator and a calibration unit is provided. The voltage regulator regulates an output voltage according to a reference voltage and a feedback voltage. The feedback voltage is in direct proportion to the output voltage. The calibration unit is coupled to the voltage regulator. The calibration unit generates a control code through binary search according to the output voltage and a target voltage. The control code determines the proportion of the feedback voltage to the output voltage.

Abstract: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.