Patents Assigned to Faraday Technology Corp.
  • Publication number: 20150189182
    Abstract: A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector.
    Type: Application
    Filed: March 19, 2014
    Publication date: July 2, 2015
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Hsiu-Wei Ho, Ho-Yi Chiang
  • Publication number: 20150187051
    Abstract: In a method for estimating image noise, plural sample blocks of an image are determined; a mean of at least one color component of each of the sample blocks and a standard deviation of at least one color component of each of the sample blocks are calculated; the sample blocks are distributed into plural segments according to the means of the sample blocks; a weighted average of the standard deviations of all of the sample blocks of each of the segments is calculated according to at least one threshold value that is determined according to the minimum standard deviation among the standard deviations of all of the sample blocks of the segment. The weighted average may be applied to noise reduction, edge detection, or motion detection of the image.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 2, 2015
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventor: Shih-Ta Wu
  • Publication number: 20150162077
    Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.
    Type: Application
    Filed: March 7, 2014
    Publication date: June 11, 2015
    Applicants: NATIONAL CHIAO TUNG UNIVERSITY, FARADAY TECHNOLOGY CORP.
    Inventors: Ching-Te Chuang, Chih-Hao Chang, Chao-Kuei Chung, Chien-Yu Lu, Shyh-Jye Jou, Ming-Hsien Tu
  • Patent number: 9054821
    Abstract: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 9, 2015
    Assignee: Faraday Technology Corp.
    Inventors: Kuan-Yu Chen, Yuan-Min Hu
  • Patent number: 9053621
    Abstract: An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: June 9, 2015
    Assignee: Faraday Technology Corp.
    Inventor: Chun-Hung Lin
  • Patent number: 9052730
    Abstract: A voltage regulator calibration circuit including a voltage regulator and a calibration unit is provided. The voltage regulator regulates an output voltage according to a reference voltage and a feedback voltage. The feedback voltage is in direct proportion to the output voltage. The calibration unit is coupled to the voltage regulator. The calibration unit generates a control code through binary search according to the output voltage and a target voltage. The control code determines the proportion of the feedback voltage to the output voltage.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: June 9, 2015
    Assignee: Faraday Technology Corp.
    Inventors: Chi-Yang Chen, San-Yueh Huang
  • Publication number: 20150131766
    Abstract: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 14, 2015
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Kuan-Yu Chen, Yuan-Min Hu
  • Publication number: 20150010213
    Abstract: An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance.
    Type: Application
    Filed: August 5, 2013
    Publication date: January 8, 2015
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventor: Chun-Hung Lin
  • Publication number: 20140310502
    Abstract: A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller. The page address history table is used to record the space size information for a plurality of page table entry which are written to the main translation look-aside buffer. The controller decides to whether access a page table entry or not from the main translation look-aside buffer according to the page address history table.
    Type: Application
    Filed: May 28, 2013
    Publication date: October 16, 2014
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventor: Tung-Yao Lee
  • Patent number: 8854897
    Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 7, 2014
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
  • Patent number: 8831151
    Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: September 9, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chien-Heng Wong, Ming-Shih Yu
  • Patent number: 8749931
    Abstract: An electrostatic discharge (ESD) protection apparatus includes at least one first transistor and at least one second transistor. The first transistor includes a control terminal, a first terminal, a second terminal, and a bulk. The control terminal and the second terminal of the first transistor are coupled to each other. The first terminal of the first transistor is coupled to one of a pad and a power rail line. Likewise, the second transistor also includes a control terminal, a first terminal, and a second terminal. The first terminal of the second transistor is coupled to the bulk of the first transistor, the bulk of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the other of the pad and the power rail line.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: June 10, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Chia-Ku Tsai, Yan-Hua Peng, Ming-Dou Ker
  • Patent number: 8743517
    Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Yan-Hua Peng, Chia-Ku Tsai, Ming-Dou Ker
  • Publication number: 20140146231
    Abstract: A display apparatus and an image capturing method are provided. The display apparatus includes a receiving unit, a processing unit, a display panel, a display output interface, and a capturing unit. The receiving unit is coupled to a data bus and receives video stream data provided by an external video source. The processing unit is coupled to the data bus and processes the video stream data to generate display data. The display output interface is coupled to the processing unit and the display panel, receives the display data, and drives the display panel to display an image frame. The capturing unit is coupled to the data bus and captures all or part of the image frame according to a capturing command issued by an external device, so as to obtain captured target data. The capturing unit also transmits the captured target data back to the external device.
    Type: Application
    Filed: January 31, 2013
    Publication date: May 29, 2014
    Applicant: Faraday Technology Corp.
    Inventors: Liang-Ting Lin, Hung-Chun Yang, Shan-Tai Chen
  • Patent number: 8730634
    Abstract: Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Chia-Ku Tsai, Fu-Yi Tsai, Yan-Hua Peng
  • Patent number: 8724762
    Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: May 13, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Yen-Yin Huang, Chauo-Min Chen, Kuan-Yu Chen, Yu-Sheng Yi, Ming-Shih Yu
  • Patent number: 8659936
    Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: February 25, 2014
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Wei Hwang, Chia-Cheng Chen, Wei-Chiang Shih
  • Patent number: 8656103
    Abstract: A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 18, 2014
    Assignee: Faraday Technology Corp.
    Inventors: Hui-Chin Yang, Shun-Chieh Chang, Guan-Ying Chiou, Chung-Ping Chung
  • Patent number: 8564263
    Abstract: A voltage regulator includes a constant voltage power circuit and an overcurrent protection circuit. The constant voltage power circuit generates an output voltage, an output current and a divided voltage. The overcurrent protection circuit includes a current sensing unit, a first mirroring unit, a voltage to current converting unit, a second mirroring unit, and a pull up unit. The current sensing unit generates a sensing current according to the output current. The first mirroring unit generates a first mirroring current. The first mirroring current is proportional to the output current. The voltage to current converting unit is used for converting the divided voltage into a first current. The second mirroring unit generates a second mirroring current. The second mirroring current is proportional to the second current. The pull up unit controls the output voltage and the output current according to the first mirroring current and the second mirroring current.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 22, 2013
    Assignee: Faraday Technology Corp.
    Inventor: Chi-Yang Chen
  • Patent number: 8520793
    Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: August 27, 2013
    Assignee: Faraday Technology Corp.
    Inventors: Chun-Cheng Lin, Ming-Shih Yu