Patents Assigned to Foundry Networks, Inc.
  • Publication number: 20090290499
    Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
    Type: Application
    Filed: March 9, 2009
    Publication date: November 26, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Chang, Yuen Fai Wong
  • Publication number: 20090287952
    Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
    Type: Application
    Filed: March 9, 2009
    Publication date: November 19, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Z. Chang, Yuen Fai A. Wong
  • Publication number: 20090282322
    Abstract: Embodiments of the present invention provide techniques for efficient generation of CRC values in a network environment. Specific embodiments of the present invention enable CRC processing circuits that can generate CRC values at high data throughput rates (e.g., 100 Gbps or greater), while being capable of being implemented on currently available FPGAs. Accordingly, embodiments of the present invention may be used in network devices such as routers, switches, hubs, host network interfaces and the like to support high speed data transmission standards such as 100G Ethernet and beyond.
    Type: Application
    Filed: July 18, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Hui Zhang
  • Publication number: 20090279549
    Abstract: Disclosed is a technique for facilitating software upgrade for a switching system comprising a first management processor and a second management processor and a set of one or more line processors, the techniques comprising receiving a signal to perform a software upgrade for a line processor from the set of line processors, and performing a software upgrade for the line processor without substantially affecting packet switching performed by the switching system.
    Type: Application
    Filed: December 27, 2006
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Rajiv Ramanathan, Ron Talmor, Shao-Kong Kao, Anthony Ho, Rudramahesh Rugge
  • Publication number: 20090279548
    Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.
    Type: Application
    Filed: January 8, 2007
    Publication date: November 12, 2009
    Applicant: FOUNDRY NETWORKS, INC.
    Inventors: Ian Edward Davis, Aris Wong
  • Publication number: 20090279423
    Abstract: Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU.
    Type: Application
    Filed: July 31, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Ravindran Suresh, Adoor V. Balasubramanian
  • Publication number: 20090279542
    Abstract: Techniques are provided for assisting in the processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. The processing is performed using dual memory structures that enable receipt of FDP packets by the network device to be decoupled from the processing of FDP packets by the CPU of the network device.
    Type: Application
    Filed: December 10, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Pedman Moobed
  • Publication number: 20090279541
    Abstract: Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, a module is provided in a network device for detecting and flagging the non-receipt of FDP packets by the network device for one or more FDP sessions. In this manner, the task of detecting non-receipt of FDP packets is offloaded from the CPU of the network device. This enables the network device to support newer FDPs with shorter periodic interval requirements.
    Type: Application
    Filed: December 10, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Pedman Moobed
  • Publication number: 20090279441
    Abstract: Techniques are provided for processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. The task of transmitting FDP packets from a network device is offloaded from the CPU of the network device and instead handled by another module of the network device. In this manner, the processing that the CPU of the network device has to perform for transmitting FDP packets for the various FDP sessions of the network device is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.
    Type: Application
    Filed: December 10, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Pedman Moobed
  • Publication number: 20090279561
    Abstract: A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.
    Type: Application
    Filed: February 17, 2009
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Andrew Chang, Ronak Patel, Ming G. Wong
  • Publication number: 20090282148
    Abstract: Embodiments of the present invention provide techniques for efficient generation of CRC values in a network environment. Specific embodiments of the present invention enable CRC processing circuits that can generate CRC values at high data throughput rates (e.g., 100 Gbps or greater), while being capable of being implemented on currently available FPGAs. Accordingly, embodiments of the present invention may be used in network devices such as routers, switches, hubs, host network interfaces and the like to support high speed data transmission standards such as 100G Ethernet and beyond.
    Type: Application
    Filed: July 18, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Hui Zhang
  • Publication number: 20090279440
    Abstract: Techniques that assist in processing of failure detection protocol (FDP) packets. Techniques are provided that assist a CPU of a network device in processing incoming FDP packets. In one embodiment, only a subset of FDP packets received by the network device is forwarded to the CPU for processing, the other FDP packets are dropped and not forwarded to the CPU. In this manner, the amount of processing that a CPU of the network device has to perform for incoming FDP packets is reduced. This enables the network device to support newer FDPs with shorter periodic interval requirements.
    Type: Application
    Filed: December 10, 2007
    Publication date: November 12, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Yuen Wong, Pedman Moobed
  • Publication number: 20090276601
    Abstract: A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 5, 2009
    Applicant: Foundry Networks, Inc.
    Inventor: Mani Prasad Kancherla
  • Publication number: 20090275328
    Abstract: Wireless roaming in a computer network may be handled through a solution provided on one or more switches in the network. A roam request sent by a switch corresponding to the user's new location may be received by the other switches in the network. If the user is known to any of these switches, then they may execute steps to accommodate the roaming. The tasks performed may vary based on whether the roaming is on layer 2 or layer 3, whether the switch is a home agent for the client, and/or whether the switch already corresponds to the user's new location.
    Type: Application
    Filed: October 31, 2008
    Publication date: November 5, 2009
    Applicant: FOUNDRY NETWORKS, INC.
    Inventor: Vishal Sinha
  • Patent number: 7613183
    Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: November 3, 2009
    Assignee: Foundry Networks, Inc.
    Inventors: Tony M. Brewer, Harry C. Blackmon, Chris Davies, Harold W. Dozier, Thomas C. McDermott, III, Steven J. Wallach, Dean E. Walker, Lou Yeh
  • Publication number: 20090265785
    Abstract: A system and method that provides for copying ARP replies, and generating data packets which include the ARP reply, and other information such as an identification of the port on the ARP reply was received. These data packets are then transmitted to an ARP collector which stores the ARP reply and port information. The ARP collector then uses this stored information, and analyzes future data packets relative to the stored information to detect occurrences of ARP spoofing. The ARP collector further provides for generating alerts and taking security actions when ARP reply spoofing is detected.
    Type: Application
    Filed: June 4, 2009
    Publication date: October 22, 2009
    Applicant: Foundry Networks, Inc.
    Inventor: Philip Kwan
  • Publication number: 20090260083
    Abstract: A system and method that provides for using source IP addresses and MAC addresses in a network to provide security against attempts by users of the network to use false source IP addresses in data packets. The system and method provide for analyzing MAC addresses and source IP addresses at the datalink (layer 2) level, and to use the information derived from such analysis to block access through a port where a host device is using a false, or spoofed, source IP address in transmitted data packets. Further, the system and method provide for validating initially learned source IP addresses, and for determining whether the number of unsuccessful attempts to validate new source IP addresses exceeds a threshold level, and where the number does exceed the threshold number the system and method can provide for operation in a possible attack mode.
    Type: Application
    Filed: February 25, 2009
    Publication date: October 15, 2009
    Applicant: Foundry Networks, Inc.
    Inventors: Ronald W. Szeto, Nitin Jain, Ravindran Suresh, Philip Kwan
  • Publication number: 20090254973
    Abstract: A system and method that provides for using source IP addresses and MAC addresses in a network to provide security against attempts by users of the network to use false source IP addresses in data packets. The system and method provide for analyzing MAC addresses and source IP addresses at the datalink (layer 2) level, and to use the information derived from such analysis to block access through a port where a host device is using a false, or spoofed, source IP address in transmitted data packets.
    Type: Application
    Filed: February 25, 2009
    Publication date: October 8, 2009
    Applicant: Foundry Networks, Inc.
    Inventor: Philip Kwan
  • Patent number: 7596139
    Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: September 29, 2009
    Assignee: Foundry Networks, Inc.
    Inventors: Ronak Patel, Ming G. Wong, Yu-mei Lin, Andrew Chang
  • Patent number: 7594093
    Abstract: A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: September 22, 2009
    Assignee: Foundry Networks, Inc.
    Inventor: Mani Prasad Kancherla