Patents Assigned to Fuji Electric Co., Ltd.
  • Patent number: 11894791
    Abstract: A control device includes a control circuit configured to control an inverter circuit that drives a motor by a plurality of switching elements coupled between DC buses, a first power supply system using a voltage source different from the DC buses as a power supply, a second power supply system using the DC buses as a power supply, and a switching circuit configured to switch a power supply system that supplies power to the control circuit from the first power supply system to the second power supply system when an abnormality in the first power supply system is detected. The control circuit continues control of the inverter circuit with a power consumption lower than that before the abnormality is detected in the first power supply system, when the abnormality is detected.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 6, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaki Hirakata
  • Publication number: 20240039390
    Abstract: A semiconductor device includes a main circuit and a control circuit. The main circuit includes a plurality of series circuits that are connected in parallel to one another. Each series circuit includes a high-side switching element and a low-side switching element that are connected in series. The control circuit includes first to third input terminals through which a serial drive signal serving as a driving signal of each high-side switching element and each low-side switching element is inputted, a first clock signal, and a second clock signal are respectively inputted, and a plurality of output terminals. The control circuit holds the serial drive signal based on the first clock signal, and based on the second clock signal outputs, to each high-side switching element and each low-side switching element, parallel signals generated from the serial drive signal.
    Type: Application
    Filed: June 29, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Atsuya KOIKE
  • Publication number: 20240038750
    Abstract: A semiconductor module includes: first and second switching devices coupled in series; a casing housing the first and second switching devices, and having first to fourth edges respectively on first to forth edge sides thereof; positive and negative terminals provided on the first edge side of the casing; an output terminal provided on the second edge side of the casing; a first control terminal and a first sense terminal for the first switching device, and a second control terminal and a second sense terminal for the second switching device, all provided on the third edge side of the casing; first and second conductive patterns respectively coupled to the positive terminal and the output terminal, and on which the first and second switching device are respectively arranged; and a third conductive pattern coupled to the negative terminal and the second switching device, on a side corresponding to the fourth edge side.
    Type: Application
    Filed: June 28, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takuma SAKAI, Seiki IGARASHI
  • Publication number: 20240038643
    Abstract: A semiconductor device includes: an isolation circuit board; a semiconductor chip provided on one main surface of the isolation circuit board; a first external terminal having a main surface and including a first snubber connecting portion rising from the main surface of the first external terminal, the first external terminal being electrically connected to the semiconductor chip; a second external terminal placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal, and including a second snubber connecting portion rising from the main surface of the second external terminal, the second external terminal being electrically connected to the semiconductor chip; and a capacitor having one end connected to the first snubber connecting portion and the other end connected to the second snubber connecting portion
    Type: Application
    Filed: June 29, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Ryusuke KATO
  • Publication number: 20240039395
    Abstract: An integrated circuit for a power supply circuit that includes a detection resistor. The integrated circuit includes: a first pad; a first terminal coupled to the detection resistor, the first terminal being electrically connected to the first pad in a first case, and being electrically separated from the first pad in a second case; a first temperature detection circuit having a temperature detection element, and being configured to detect a first temperature based on a voltage of the temperature detection element; a second temperature detection circuit configured to detect a second temperature of the integrated circuit, based on a first voltage corresponding to a resistance value of the detection resistor, received through the first pad in the first case; and a circuit configured to operate based on results of detection of the second and first temperature detection circuits, respectively in the first case and in the second case.
    Type: Application
    Filed: June 27, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshinori KOBAYASHI
  • Publication number: 20240038851
    Abstract: A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.
    Type: Application
    Filed: September 28, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Shinsuke HARADA
  • Patent number: 11887941
    Abstract: Provided is a semiconductor module, including: a semiconductor chip; a circuit board on which the semiconductor chip is mounted; a sealing resin including epoxy resin for sealing the semiconductor chip and the circuit board; and a reinforcing material, with a higher Young's modulus than the sealing resin, provided in close contact with the sealing resin above at least a part of the sealing resin. The semiconductor module includes a resin case for enclosing spaces for housing the semiconductor chip, wherein the sealing resin may be provided inside the resin case.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomohiro Nishimura
  • Patent number: 11887902
    Abstract: A first wiring member bends at a first bent portion in the shape of the letter “L” in a side view and includes a first horizontal portion parallel to the principal surface of a semiconductor chip and a first vertical portion perpendicular to the first horizontal portion. A second wiring member bends at a second bent portion in a direction opposite to the first wiring member in the shape of the letter “L” in the side view and includes a second horizontal portion flush with the first horizontal portion and a second vertical portion a determined distance distant from the first vertical portion and parallel to the first vertical portion. A wiring holding portion fills a gap between the first and second vertical portions and a gap between the first and second bent portions. Therefore, stress applied to the vicinity of the first or second bent portion is relaxed.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Satoshi Kaneko
  • Patent number: 11887925
    Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Yuma Murata
  • Patent number: 11888035
    Abstract: The silicon carbide semiconductor device includes: a silicon carbide layer; a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen; and a transition region arranged between the silicon carbide layer and the silicon dioxide layer, and containing carbon, oxygen, and nitrogen, wherein the maximum nitrogen concentration in the transition region is 1.0×1020 cm?3 or higher. The maximum nitrogen concentration in the transition region is five or more times higher than the maximum nitrogen concentration in the silicon dioxide layer.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Aki Takigawa
  • Publication number: 20240030078
    Abstract: A semiconductor module includes: a laminated substrate configured by laminating an insulating plate, a heat dissipation plate disposed on a lower surface of the insulating plate, and a circuit plate disposed on an upper surface of the insulating plate; a semiconductor element disposed on an upper surface of the circuit plate; a case that surrounds the laminated substrate and a space housing the semiconductor element; a sealing resin filling the space of the case to seal the semiconductor element; and a partition wall that extends in an up-down direction to divide the space filled with the sealing resin into a plurality of subspaces. The partition wall has a lower end and an upper end opposite to each other in the up-down direction. At least a portion of the lower end of the partition wall is connected to the upper surface of the circuit plate.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki HAYASHI
  • Publication number: 20240027328
    Abstract: The generated amount of silica scale under complicated conditions is accurately predicted.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tianlong JIANG, Takayuki HIROSE, Azusa WADA, Shinya UI
  • Publication number: 20240030211
    Abstract: A semiconductor module includes at least, a conductive pattern on the insulating substrate; a first semiconductor element on the conductive pattern, a second semiconductor element on the conductive pattern, a first power collecting portion connected to a first output electrode of the first semiconductor element with a first line; and a second power collecting portion connected to a second output electrode of the second semiconductor element with a second line. Each of the first and second semiconductor elements includes both a switching element and a diode. The conductive pattern is provided between the first power collecting portion and the second power collecting portion. A current path length from a first output electrode of the first semiconductor element to the first power collecting portion and a current path length from a second output electrode of the second semiconductor element to the second power collecting portion are equal to each other.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 25, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hiroyuki NOGAWA
  • Patent number: 11879930
    Abstract: A test circuit for testing a switching device. The test circuit includes: a first terminal for receiving a drive signal; second, third and fourth terminals respectively coupled to a ground electrode, a control electrode and a power-supply electrode, of the switching device; and a clamping circuit coupled between the second terminal and the fourth terminal. The clamping circuit is configured to, upon turning on of the switching device responsive to the drive signal, cause a voltage at the third terminal to be a first voltage higher than a threshold of the switching device, and, upon turning off of the switching device responsive to the drive signal, cause the voltage at the third terminal to be a third voltage between the threshold and the first voltage, while clamping a voltage at the fourth terminal to a second voltage lower than a withstand voltage of the switching device.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: January 23, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuru Yoshida
  • Publication number: 20240022176
    Abstract: An integrated circuit for a power supply circuit. The integrated circuit includes: a first terminal to which a first resistor, a second resistors, and a switch, of the power supply circuit are coupled; a current output circuit outputting a current to the first terminal; a switch control circuit causing the switch to be in a first state or a second state, in which a voltage according to the first resistor or the second resister are respectively applied to the first terminal; a storage circuit; a processing circuit storing an operating condition of the integrated circuit in the storage circuit, based on a first voltage at the first terminal when the switch is in the first state; and a temperature detection circuit detecting a temperature, based on a second voltage at the first terminal when the switch is in the second state.
    Type: Application
    Filed: May 22, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshinori KOBAYASHI
  • Publication number: 20240021605
    Abstract: A semiconductor device includes a main semiconductor region and a current detecting region. The main semiconductor region and the current detecting region have a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type, first semiconductor regions of a second conductivity type, second semiconductor regions of the first conductivity type, trenches, first high-concentration regions of the second conductivity type, and second high-concentration regions of the second conductivity type. An active region through which a current flows when the current detecting region is in an on-state has a first cell region that operates as a transistor and second cell regions that are provided, respectively, in four corners of the first cell region and operate only as diodes and not as a transistor.
    Type: Application
    Filed: May 31, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Keishirou KUMADA
  • Publication number: 20240021569
    Abstract: A semiconductor module includes a stacked substrate includes an insulating plate and first and second circuit boards arranged on the insulating plate, a semiconductor element arranged on the first circuit board, and a metal wiring board having a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material. The first bonding portion includes a first plate-shaped portion that has at a lower surface thereof, a boss protruding toward the semiconductor element, and at an upper surface thereof, a first recess at a position corresponding to a position immediately above the boss and multiple second recesses. At the upper surface of the first plate-shaped portion, each of the second recesses has an opening area smaller than an opening area of the first recess.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko NAKAMURA, Akihiko IWAYA, Mai SAITO, Tsubasa WATAKABE
  • Publication number: 20240021723
    Abstract: In an intermediate region between an active region and an edge termination region, on a front surface of a semiconductor substrate, a gate polysilicon wiring layer is provided via an insulating layer in which a gate insulating film and a field oxide film are stacked sequentially. An inner peripheral end of the field oxide film is positioned directly beneath the gate polysilicon wiring layer, which extends inward from the field oxide film and terminates on the gate insulating film. At the surface of the insulating layer directly beneath the gate polysilicon wiring layer, on the inner peripheral end of the field oxide film, a drop is formed by a difference in thickness due to whether the field oxide film is present. A distance from the drop to a contact hole of the active region is 21 ?m or less.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Tomohiro MORIYA
  • Publication number: 20240021737
    Abstract: A silicon carbide semiconductor device has an active region, a first-conductivity-type region, and an edge termination region. The active region has first second-conductivity-type regions, a silicide film, and a first electrode; the edge termination region has a second second-conductivity-type region. The active region is configured by an ohmic region in which the silicide film is in contact with the first second-conductivity-type region, non-operating regions in which the first electrode is in contact with the first second-conductivity-type regions, and a Schottky region in which the first electrode is in contact with the first-conductivity-type region. The ohmic region, the non-operating regions, and the Schottky regions are provided in a striped pattern. A bottom surface of the silicide film in the ohmic region is positioned deeper than is an interface between the first electrode and the first second-conductivity-type regions in each of the plurality of non-operating regions.
    Type: Application
    Filed: May 29, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi HASHIZUME
  • Publication number: 20240021720
    Abstract: P++-type contact regions are disposed apart from one another, and in a p?-type base region, at least hole current regions directly beneath the contact regions have an impurity concentration of not more than 5×1016/cm3. A p+-type region for mitigating electric field and disposed between adjacent gate trenches is separated into first portions in contact with the hole current regions and second portions in contact with only a portion of the base region other than the hole current regions. During conduction of body diodes, forward current flows into an n?-type drain region through the contact regions, the hole current regions, and the first portions. Thus, in the drain region, holes from the base region are injected only into hole injection regions that are directly beneath the first portions, but are not injected into regions that respectively surround peripheries of the hole injection regions.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 18, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takashi TSUJI