Patents Assigned to Fujitsu Semiconductor Limited
  • Publication number: 20170186704
    Abstract: A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 29, 2017
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Jun Sakuma, Hideaki Matsumura, Tadashi Ohshima
  • Patent number: 9691767
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 27, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
  • Patent number: 9685442
    Abstract: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 20, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Makoto Yasuda, Mitsuaki Hori
  • Patent number: 9685416
    Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: June 20, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutaka Yoshizawa, Taiji Ema
  • Patent number: 9680470
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 13, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 9679904
    Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 13, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Patent number: 9634021
    Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 25, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
  • Patent number: 9619235
    Abstract: A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 11, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Mitsuru Tomono, Hiroya Uehara, Makiko Ito
  • Patent number: 9614482
    Abstract: An amplifier includes two input terminals to receive a differential, two-tone transmission signal; two output terminals; a coil having terminals connected with the input terminals respectively, and a center tap; a first transistor having the gate connected with one terminal of the coil, and the output terminal connected with one output terminal; a second transistor having the gate connected with the other terminal of the coil, and the output terminal connected with the other output terminal; a diode having a terminal connected with the center tap; and a bias circuit connected with the other terminal of the diode to output a gate voltage to turn on the first and second transistors. The diode adjusts the terminal voltage depending on a signal level of a double harmonic wave of the transmission signal supplied to the terminal of the diode from the center tap.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: April 4, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yoichi Kawano, Shinji Yamaura
  • Publication number: 20170062283
    Abstract: There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yasunobu Torii
  • Patent number: 9583484
    Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 28, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: David A. Kidd
  • Patent number: 9577041
    Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 21, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R. Sonkusale
  • Publication number: 20170047246
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hirosato OCHIMIZU, Atsuhiro TSUKUNE, Hiroshi KUDO
  • Patent number: 9559058
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 31, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Patent number: 9548086
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 17, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Patent number: 9543228
    Abstract: A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 10, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kouichi Kanda, Nobumasa Hasegawa
  • Patent number: 9524899
    Abstract: There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 20, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yasunobu Torii
  • Patent number: 9514940
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Patent number: 9508728
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: November 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson
  • Patent number: 9508800
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson