Abstract: A real time video processing system adds a programmable logic device between a conventional frame buffer and a conventional digital to analog converter to provide real time and off-screen processing power to enhance video output capabilities. The system may include a history FIFO connected to deliver the preceding line to the programmable logic device, allowing operations on a pixel in the current line, modified as needed by the status of one or more nearby pixels. The system may also include inputs for multiple video sources and may include input FIFOs for more random access to portions of the input stream. An alternative form of the system includes a crossbar switch and multiple memory devices, to allow switching among several possible frame buffer devices. One or more processing units can be added to manipulate a memory which is not the active frame buffer. The programmable logic device can be loaded with a configuration file stored in an associated memory or loaded from a host computer.

Abstract: A method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow in the scheme, providing for at least two connected system resources to implement the logic scheme, selecting an op code, and providing a way to implement the various components needed to call and execute the function according to the logic scheme. A useful op code may invoke a system resource, implement the logic scheme, pass a parameter to the function, or invoke the function. The configurable hardware system can function as a CPU, using logic resources including a next address RAM, one or more registers, a function execution controller, and one or more busses for passing signals and data between the components and functions.

Abstract: A configurable hardware system for implementing an algorithmic language program, including at least two programmable logic devices (PLD), a private hardware resource connectible to one PLD, and a programmable connection between PLDs, all of which may be configured as a module or distributed processing units (DPU). The private hardware resource may include a serial processing device such as a DSP, a PLD, a memory device, or a CPU. An extensible processing unit (EPU) can be built out of multiple DPUs, each connected to other modules by one or more of several buses. An N-bus (neighbor bus) connects a module to its nearest neighbor, an M-bus (module bus) connects a group of modules, and an H-bus (host bus) connects a module to a host CPU. The invention also includes a method of translating source code in an algorithmic language into a configuration file for implementation on one or more DPUs.

Abstract: A module for supporting and connecting programmable logic devices through a common interface. A card in the PC Card format is provided with bus interface support for interconnection to other such modules. The module supports one or more programmable logic devices, each of which is connectable to four connectors, two each on top of the module, two each on the bottom of the module. Each connector includes a plurality of pins for electrical signals. These signals include one or more progammable buses, structured to form an expansible system. In a preferred embodiment, the buses include multiple, distinct, programmable buses.

Abstract: A video processing module designed for high performance using economical components. A programmable logic device (PLD) is configured to modify a data stream, in particular a video stream. The PLD can be connected to a memory resource. In addition, the PLD can be connected to a second PLD through an interruptable connection. The second PLD can be optimized for bus interface communication and connected to an external system, typically a host computer. The second PLD can take commands from the host to prepare a processing configuration for the first PLD and can connect when needed to download a configuration to the first PLD through the interruptable connection. An array of these modules can be connected in a systolic array to provide powerful, pipelined video processing.