Patents Assigned to GLOBALFOUNDRIES Inc.
  • Patent number: 10832966
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Patent number: 10832842
    Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Jagar Singh
  • Patent number: 10833153
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qizhi Liu, Steven M. Shank, John J. Ellis-Monaghan, Anthony K. Stamper
  • Patent number: 10833169
    Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tao Chu, Rongtao Lu, Ayse M. Ozbek, Wei Ma, Haiting Wang
  • Patent number: 10832944
    Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Chanro Park, Ruilong Xie, Andre P. Labonte
  • Patent number: 10833067
    Abstract: A structure includes a first dielectric over a trench silicide (TS) contact and over a gate structure, and at least one cavity in the first dielectric. A metal resistor layer is on a bottom and sidewalls of the at least one cavity and extends over the first dielectric. A first contact is on the metal resistor layer over the first dielectric; and a second contact is on the metal resistor layer over the first dielectric. The metal resistor layer is over the TS contact and over the gate structure. Where a plurality of cavities are provided in the dielectric, a resistor structure formed by the metal resistor layer may have an undulating cross-section over the plurality of cavities and the dielectric.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Scott H. Beasor, Zhenyu Hu
  • Patent number: 10831977
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mohamed Elsayed Mohamed Lotfy Gheith, Ian Stobert, Ayman Hamouda
  • Patent number: 10832839
    Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Scott Beasor, Haiting Wang, Sipeng Gu, Jiehui Shu
  • Patent number: 10832967
    Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Garo Jacques Derderian
  • Patent number: 10825897
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Patent number: 10826476
    Abstract: Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Barry L. Stakely
  • Patent number: 10825913
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Ruilong Xie
  • Patent number: 10825811
    Abstract: A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoming Yang, Sipeng Gu, Jeffrey Chee, Keith H. Tabakman
  • Patent number: 10825741
    Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10825910
    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Shesh Mani Pandey
  • Publication number: 20200342918
    Abstract: Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Anoop Delampady, Puneet Suri
  • Patent number: 10818528
    Abstract: Self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers. The wafer carrier system may include a housing configured for transport within the automated material handling system. A support is configured to support a semiconductor wafer within a housing. A metrology system is disposed within the housing. The metrology system is operable to measure at least one characteristic of the wafer. The metrology system may include a sensing unit and a computing unit operably connected to the sensing unit.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abner Bello, Stephanie Waite, William J. Fosnight, Thomas Beeg
  • Patent number: 10816728
    Abstract: Structures for a polarizer and methods of fabricating a structure for a polarizer. A first waveguide core has a first width, and a polarizer includes a second waveguide core having a second width that is greater than the first width. The second waveguide core is coupled to the first waveguide core. The polarizer includes a layer that is positioned adjacent to a side surface of the second waveguide core. The layer is comprised of a material having a permittivity with an imaginary part that ranges from 0 to about 15.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Patent number: 10818498
    Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Haiting Wang, Hui Zang
  • Patent number: 10819110
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Manjunatha G. Prabhu, Alain F. Loiseau, Mahbub Rashed, Sushama Davar