Patents Assigned to GlobalFoundries U.S. 2 LLC
  • Patent number: 9181440
    Abstract: An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The electrically conductive paste including a resin compound is formed by mixing the mixture in a high shear mixer. The electrically conductive paste can be applied to a surface of an article to form a coating, or can be molded into an article. The solvent is evaporated, and the electrically conductive paste is cured to provide a graphite-containing resin compound. The graphite-containing resin compound is electrically conductive, and provides low alpha particle emission at a level suitable for a low alpha particle emissivity coating.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Michael A. Gaynes, Michael S. Gordon, Eric P. Lewandowski
  • Patent number: 9185807
    Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 9176855
    Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include configuring one or more storage devices as a plurality of physical storage units, each of the physical storage units having a storage granularity, and configuring, on the one or more storage devices, a thin provisioned storage pool having a physical number of the physical storage units and a logical number of logical storage units, the physical number being less than the logical number. Upon receiving a request to create a thick data volume having a requested number of the physical storage units, an available number of the physical storage units that are available in the thin provisioned pool can be identified. Upon determining that the requested number is less than the available number, the requested number of the physical storage units can be allocated, from the thin provisioned storage pool, to the thick data volume.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Daniel I. Goodman, Rivka M. Matosevich, Orit Nissan-Messing
  • Patent number: 9178495
    Abstract: Embodiments of the present invention disclose a semiconductor structure and method for establishing a thermal profile across a semiconductor chip. In certain embodiments, the semiconductor structure comprises a through-silicon via formed in a first semiconductor chip having thermal control circuitry, wherein the through-silicon via is formed in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, and wherein the through-silicon via conducts heat from the thermal control circuitry to the region. In other embodiments, the method comprises forming a through-silicon via in a first semiconductor chip having thermal control circuitry. The method also comprises forming the through-silicon via in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, wherein the through-silicon via conducts heat from the thermal control circuitry to the region.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Terence B. Hook, Christopher M. Schnabel, Melanie J. Sherony
  • Patent number: 9176184
    Abstract: Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or an interposer (IP) can be used with existing equipment. Each control device can include a regulator, such as a latchable array of field effect transistors that can regulate power delivered to a respective package connector.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Mark D. Knox, Kirk D. Peterson, Esuasi K. Segbefia
  • Patent number: 9176833
    Abstract: A system, and computer program product for tolerating failures using concurrency in a cluster are provided in the illustrative embodiments. A failure is detected in a first computing node serving an application in a cluster. A subset of actions is selected from a set of actions, the set of actions configured to transfer the serving of the application from the first computing node to a second computing node in the cluster. A waiting period is set for the first computing node. The first computing node is allowed to continue serving the application during the waiting period. During the waiting period, concurrently with the first computing node serving the application, the subset of actions is performed at the second computing node. Responsive to receiving a signal of activity from the first computing node during the waiting period, the concurrent operation of the second computing node is aborted.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Douglas Griffith, Angela Astrid Jaehde, Matthew Ryan Ochs
  • Patent number: 9177931
    Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Stephen P. Ayotte, Sebastien Quesnel, Glen E. Richard, Timothy D. Sullivan, Timothy M. Sullivan
  • Patent number: 9178012
    Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Veeraraghavan S. Basker, Richard Q. Williams
  • Patent number: 9177820
    Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 9178838
    Abstract: A system, and computer program product for hash perturbation with queue management in data communication are provided. Using a first set of old queues corresponding to a first hash function, a set of data packets corresponding to a set of session is queued. At a first time, the first hash function is changed to a second hash function. A second set of new queues is created corresponding to the second hash function. A data packet is dequeued from a first old queue in a set of old queues. A second data packet is selected from a second queue in the set of old queues. A new hash value is computed for the second data packet using the second hash function. The second data packet is queued in a first new queue such that the second packet is in position to be delivered first from the first new queue.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventor: Paul Edward McKenney
  • Patent number: 9178827
    Abstract: Aspects of the invention are provided for rate control and management of service requests. A token bucket is employed in conjunction with a capacity sharing scheme to manage processing of service requests. Each token represents the capacity reserved for a particular source of requests. Excess tokens may be shed, with the excess tokens representing available excess capacity. Similarly, a projected time at which the service request(s) may be released may be computed in the event the bucket does not contain the required quantity of tokens to process the request.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Marc A. Kaplan, Anna S. Povzner
  • Patent number: 9176834
    Abstract: A method is provided in the illustrative embodiments. A failure is detected in a first computing node serving an application in a cluster. A subset of actions is selected from a set of actions, the set of actions configured to transfer the serving of the application from the first computing node to a second computing node in the cluster. A waiting period is set for the first computing node. The first computing node is allowed to continue serving the application during the waiting period. During the waiting period, concurrently with the first computing node serving the application, the subset of actions is performed at the second computing node. Responsive to receiving a signal of activity from the first computing node during the waiting period, the concurrent operation of the second computing node is aborted.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Douglas Griffith, Angela Astrid Jaehde, Matthew Ryan Ochs
  • Patent number: 9176849
    Abstract: An exemplary method includes performing a first static analysis to locate elements within a program and instrumenting the program to enable a subsequent dynamic analysis based on the located elements. The method includes executing the instrumented program and performing during execution analysis to determine individual sets of statements in the program affected by a corresponding element. The method includes partitioning the sets of statements into partitions based on one or more considerations, each partition including one or more of the elements. The method includes performing a second static analysis on the partitions of the program to produce results and outputting the results. The method may be performed for, e.g., security (e.g., taint) analysis, buffer overflow analysis, and typestate analysis. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries U.S. 2 LLC
    Inventors: Omer Tripp, Marco Pistoia, Salvatore A. Guarnieri
  • Patent number: 9171645
    Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Geovanny Rodriguez, Brian J. Vincent, Timothy J. Vonreyn
  • Patent number: 9172550
    Abstract: A system and method are provided for of a Multicast system by a controller in a software defined network. The method may include, receiving a request for a multicast stream from a first switch of the software defined network. The request may have originated from a requestor using an Internet Group Management Protocol (IGMP). The method may further include, adding the request to a table, wherein the table is designated to have requests from IGMP using requestors for multicast streams. The method may further include, determining whether the request for the multicast stream matches with a multicast data transmission from a sender received by the controller. The method may further include, initiating a connection of the multicast between the requestor and the sender if the request matches the multicast data transmission.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC COMPANY
    Inventors: Ashish Kapur, Vishal Shukla
  • Patent number: 9171971
    Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, William J. Murphy, Kirk D. Peterson, Steven M. Shank
  • Patent number: 9172025
    Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, are provided. The structure includes a single crystalline beam formed from a silicon layer of a silicon on insulator (SOI) substrate; insulator material coating the single crystalline beam; an upper cavity formed above the single crystalline beam, over a portion of the insulator material; a lower cavity formed in lower wafer bonded to an insulator layer of the SOI substrate, below the single crystalline beam and the insulator layer of the SOI substrate; a connecting via that connects the upper cavity to the lower cavity, the connecting via being coated with the insulator material; and a Bulk Acoustic Wave (BAW) filter or Bulk Acoustic Resonator (BAR) in electrical connection with the single crystalline beam.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: David L. Harame, Stephen E. Luce, Anthony K. Stamper
  • Patent number: 9170273
    Abstract: A method of generating a capacitance-voltage (C-V) characteristic for a discrete device formed within a semiconductor structure may include exposing first and second contact regions associated with the discrete device, coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer, and coupling the high-frequency impedance probe to a first and a second atomic force probe tip. Using an atomic force microscope, the first atomic force probe tip is coupled to the exposed first contact region and the second atomic force probe tip is coupled to the exposed second contact region. The C-V characteristic for the discrete device is then measured on the impedance analyzer, whereby the impedance analyzer applies an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the discrete device using the high-frequency impedance probe.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Terence L. Kane, Matthew F. Stanton, Michael P. Tenney
  • Patent number: 9171121
    Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Hanyi Ding, Alvin J. Joseph, Wayne H. Woods, Jr.
  • Patent number: 9170296
    Abstract: An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S.2 LLC
    Inventors: Kelly Malone, Brian L. Walsh