Patents Assigned to GlobalFoundries U.S. 2 LLC
  • Patent number: 9142564
    Abstract: Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: September 22, 2015
    Inventor: Terence B. Hook