Patents Assigned to Gyrfalcon Technology, Inc.
  • Patent number: 10192148
    Abstract: A string of Latin-alphabet based language texts is received and formed a multi-layer 2-D symbol in a computing system. The received string contains at least one word with each word containing at least one letter of the Latin-alphabet based language. 2-D symbol comprises a matrix of N×N pixels of data representing a super-character. The matrix is divided into M×M sub-matrices. Each sub-matrix represents one ideogram formed from the at least one letter contained in a corresponding word in the received string. Ideogram has a square format with a dimension EL letters by EL letters (i.e., row and column). EL is determined from the total number of letters (LL) contained in the corresponding word. EL, LL, N and M are positive integers. Super-character represents a meaning formed from a specific combination of at least one ideogram. Meaning of the super-character is learned with image classification of the 2-D symbol.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: January 29, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Charles Jin Young, Jason Z. Dong, Baohua Sun
  • Patent number: 10102453
    Abstract: A string of natural language texts is received and formed a multi-layer 2-D symbol in a first computing system. The 2-D symbol comprises a matrix of N×N pixels of data representing a “super-character”. The matrix is divided into M×M sub-matrices with each sub-matrix containing (N/M)×(N/M) pixels. N and M are positive integers, and N is preferably a multiple of M. Each sub-matrix represents one ideogram defined in an ideogram collection set. “Super-character” represents a meaning formed from a specific combination of a plurality of ideograms. The meaning of the “super-character” is learned in a second computing system by using an image processing technique to classify the 2-D symbol, which is formed in the first computing system and transmitted to the second computing system. Image process technique includes predefining a set of categories and determining a probability for associating each of the predefined categories with the meaning of the “super-character”.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 16, 2018
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Baohua Sun
  • Patent number: 10083171
    Abstract: A string of natural language texts is received and formed a multi-layer 2-D symbol in a computing system. The 2-D symbol comprises a matrix of N×N pixels of K-bit data representing a “super-character”. The matrix is divided into M×M sub-matrices with each sub-matrix containing (N/M)×(N/M) pixels. K, N and M are positive integers, and N is preferably a multiple of M. Each sub-matrix represents one ideogram defined in an ideogram collection set. “Super-character” represents a meaning formed from a specific combination of a plurality of ideograms. The meaning of the “super-character” is learned by classifying the 2-D symbol via a trained convolutional neural networks model having bi-valued 3×3 filter kernels in a Cellular Neural Networks or Cellular Nonlinear Networks (CNN) based integrated circuit.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: September 25, 2018
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Lin Yang, Patrick Z. Dong, Baohua Sun
  • Patent number: 10043095
    Abstract: Data arrangement schemes of imagery data and filter coefficients stored in a CNN based digital IC for extracting features out of an input image are disclosed. The CNN based digital IC contains NE number of CNN processing engines connected in a loop via a clock-skew circuit for cyclic data access. Imagery data and filter coefficients are arranged in a specific scheme to fit the data access pattern that the CNN based digital IC requires to operate. The specific scheme is determined based on the number of imagery data, the number of filters and the characteristics of the CNN based digital IC. The characteristics include, but are not limited to, the number of CNN processing engines, the connection direction of clock-skew circuit and the number of the I/O data bus.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: August 7, 2018
    Assignee: Gyrfalcon Technology, Inc.
    Inventors: Lin Yang, Huihua Yu
  • Patent number: 9959500
    Abstract: An integrated circuit processor having a processing unit that includes a logical circuit with multiple transistors and a top metal landing pad, and an embedded STT memory. The STT memory includes a dielectric layer formed on the top metal landing pad, an adhesion and topography planarization (ATP) layer formed on the dielectric layer, and an MTJ film layer disposed on the ATP layer. The memory may also include bit lines formed on the MTJ film layer. The ATP layer may have multiple layers such as a top layer and a bottom layer. The top layer may act as an etch stop for etching the MTJ film layer on the top. The ATP layer may have a total thickness of 500 A to 4000 A. The bit lines can be configured to send data to the logic circuit of the processing unit to perform one or more convolution neural network computations.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 1, 2018
    Assignee: GYRFALCON TECHNOLOGY INC.
    Inventors: Chyu-Jiuh Torng, Qi Dong, Lin Yang
  • Patent number: 9940534
    Abstract: Digital integrated circuit (IC) for extracting features out of input image is disclosed. The IC contains one or more identical cellular neural networks (CNN) processing engines operatively coupled to at least one I/O data bus. Each CNN processing engine includes a CNN processing block, a first set of memory buffers for storing imagery data and a second set of memory buffers for storing filter coefficients. CNN processing block is configured to simultaneously perform 3×3 convolutions at M×M pixel locations using received imagery data and corresponding filter coefficients. Imagery data represents a (M+2)-pixel by (M+2)-pixel region of the input image. CNN processing block further performs rectification and/or 2×2 pooling operations as directed. When two or more CNN processing engines are configured on the IC, CNN processing engines are connected to one another as a loop via a clock-skew circuit for cyclic data access. M is a positive integer.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: April 10, 2018
    Assignee: Gyrfalcon Technology, Inc.
    Inventors: Lin Yang, Huihua Yu