Patents Assigned to Honeywell Information Systems, Inc.
  • Patent number: 4685032
    Abstract: An electronic system is packaged to provide a single etched backplane. Bus bars are physically fastened to bushings which are soldered to the backplane power etch lines to provide power to the system.Printed circuit boards are plugged into connectors mounted on the backplane for receiving power and transferring logic signals between printed circuit boards. A number of power supplies are plugged into connectors mounted on the bus bars for transmitting power, and plugged into connectors for transferring logic signals.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: August 4, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: John W. Blomstedt, Paul S. Yoshida, Wesley F. Irving, Vladimir Roudenko
  • Patent number: 4683466
    Abstract: A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.
    Type: Grant
    Filed: December 14, 1984
    Date of Patent: July 28, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas O. Holtey, Kenneth E. Bruce, Gary J. Goss
  • Patent number: 4680702
    Abstract: A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the register to control the merging of the identified zone or zones of the associated word with the remainder of the data in the addressed word block.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: July 14, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventor: Daniel M. McCarthy
  • Patent number: 4677548
    Abstract: A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: June 30, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventor: John J. Bradley
  • Patent number: 4672360
    Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.
    Type: Grant
    Filed: September 30, 1983
    Date of Patent: June 9, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: John J. Bradley, Brian L. Stoffers, Melinda A. Widen
  • Patent number: 4670835
    Abstract: Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition.
    Type: Grant
    Filed: October 19, 1984
    Date of Patent: June 2, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Richard P. Kelly, Thomas F. Joyce
  • Patent number: 4669057
    Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.
    Type: Grant
    Filed: October 3, 1983
    Date of Patent: May 26, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Vincent M. Clark, Jr., David R. Bourgeois, Dennis W. Chasse, Todd R. Comins
  • Patent number: 4665822
    Abstract: A squeegee is utilized in a screen process printer for microcircuits and components thereof. The type is one in which the squeegee and a flat stationary screen are mounted with the squeegee movable and in a wiping action makes contact with the screen so as to press a paste through openings of the screen in a predetermined pattern onto an adjacent substrate. The squeegee comprises a cylindrically shaped object of a predetermined length having a surface covering made of a resiliently deformable material. Further, the squeegee has an external cross-sectional geometric pattern such that a first surface is pushed against the paste in the wiping action. A lower edge of the first surface is above the surface of the screen a predetermined distance, and the first surface is at a predetermined fixed angle with the screen thereby causing a spreading action of the paste on the screen surface.
    Type: Grant
    Filed: May 12, 1986
    Date of Patent: May 19, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Boris Plesinger, Lynn H. Brown
  • Patent number: 4667288
    Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.
    Type: Grant
    Filed: June 30, 1983
    Date of Patent: May 19, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: James W. Keeley, Robert V. Ledoux, Virendra S. Negi
  • Patent number: 4667329
    Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.
    Type: Grant
    Filed: November 30, 1982
    Date of Patent: May 19, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas L. Murray, Jr., James C. Siwik, Thomas O. Holtey
  • Patent number: 4665481
    Abstract: A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.
    Type: Grant
    Filed: June 13, 1983
    Date of Patent: May 12, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: James W. Stonier, Thomas L. Murray, Jr., Gary J. Goss, Thomas O. Holtey
  • Patent number: 4665482
    Abstract: A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller.
    Type: Grant
    Filed: June 13, 1983
    Date of Patent: May 12, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas L. Murray, Jr., James W. Stonier, Gary J. Goss, Thomas O. Holtey
  • Patent number: 4663733
    Abstract: Information read from a disk device includes synchronization bytes to enable a controller to get into byte synchronization with a stream of bits received from the disk. The stream of bits passes through a shift register. Firmware conditions a multiplexer which receives the parallel output of the serial register to select the high order binary ONE bit thereby enabling the controller to get into byte synchronization with the stream of bits.
    Type: Grant
    Filed: October 4, 1985
    Date of Patent: May 5, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Edward F. Getson, Jr., John W. Bradley, Bruce R. Cote
  • Patent number: 4662067
    Abstract: A connector for providing electrical connections for a coax cable harness, the coax cable harness including a plurality of coax cables, each coax cable having a wire encased in a dielectric and having a drain wire. The connector comprises an insulation displacement connector having a plurality of insulation displacement contacts set in a top surface of the insulation displacement connector. Each insulation displacement contact engages a corresponding wire encased in the dielectric, the insulation displacement contact piercing the dielectric thereby providing the electrical connection for the wire of the coax cable. An orientation bar positions the coax cables to be in line with the corresponding insulation displacement contact, the coax cables resting on a top surface of the orientation bar. The orientation bar is positioned next to the insulation displacement connector such that a side surface of the insulation displacement connector is in contact or nearly in contact with the orientation bar.
    Type: Grant
    Filed: April 7, 1986
    Date of Patent: May 5, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventor: Ronald F. Abraham
  • Patent number: 4654789
    Abstract: A chip implemented in newer technology is designed to include new functionality. The chip includes compatibility circuits which connect to a pin which is unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at higher speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with the new functionality at the same higher speed and improved performance as compared to the replaced chip.
    Type: Grant
    Filed: April 4, 1984
    Date of Patent: March 31, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Eugene Nusinov, John J. Bradley
  • Patent number: 4654788
    Abstract: A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses. Priority resolver circuits award access to main memory on a predetermined priority basis. Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits. The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors.
    Type: Grant
    Filed: June 15, 1983
    Date of Patent: March 31, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Daniel A. Boudreau, Edward R. Salas
  • Patent number: 4652730
    Abstract: A method and apparatus for skew compensation in an optical reader is described. The method provides for calculating the amount of skew between the read scan line used to read the data and the recording path line used when the data was written on the recording media. By determining the position of each end of the scan line by counting delimiter marks along the two edges of the data being read, the skew can be calculated by determining the difference in delimiter counts. The data is divided into bands along the direction of scan within which the skew will not cause trouble misreadings at the extreme bits of the scan line within a band. The data is scanned multiple times during the transition of the data strip so that at least one good read of each data band in the data strip will occur.
    Type: Grant
    Filed: January 3, 1985
    Date of Patent: March 24, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventor: J. Nathaniel Marshall
  • Patent number: 4651329
    Abstract: An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse.The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).
    Type: Grant
    Filed: January 10, 1984
    Date of Patent: March 17, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Gary J. Goss, Robert G. H. Moles, Randall D. Hinrichs, Thomas O. Holtey
  • Patent number: 4649539
    Abstract: An apparatus for storing information contained in a selected digital data signal comprises a selector. A first input terminal receives an operational digital data signal when the apparatus is operating in a normal mode, a second input terminal receives a shifted test data signal when the apparatus is operating in a maintenance mode, and a third input terminal is operatively connected to a signal having a constant reset state. The selector operatively connects one of the first, second, and third input terminals to the output terminal of the selector in response to a first and second control signal. A storage element, having a clock input terminal adapted to receive a clock signal and having a reset terminal adapted to receive a reset signal, stores the state present at the selected input terminal of the selector coincident with the clock signal.
    Type: Grant
    Filed: November 4, 1985
    Date of Patent: March 10, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Steven L. Crain, Homer W. Miller
  • Patent number: 4646260
    Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. Included among the devices is a communication controller. An interrupt controller processes the device interrupt requests by sending out a vector address to the microprocessor. This enables the microprocessor to branch to a subroutine to process the interrupt. Apparatus is provided to enable the communication controller to generate vector addresses when it sends an interrupt request to the interrupt controller.
    Type: Grant
    Filed: October 3, 1983
    Date of Patent: February 24, 1987
    Assignee: Honeywell Information Systems Inc.
    Inventors: Dennis W. Chasse, David R. Bourgeois, Todd R. Comins