Abstract: A predecoder of a semiconductor memory device which is capable of selectively inverting a signal output from a decoding unit adapted to decode internal addresses generated from address buffers, thereby achieving an improvement in the utility thereof. The predecoder includes a selection unit for selectively outputting one of the signals having different logic levels while being generated based on an output signal from the decoding unit. Where the predecoder is applied to a cell repair circuit using antifuses, it is possible to reduce the layout area of the cell repair circuit, thereby achieving a reduction in the chip size. This results in a reduction in the costs of the chip.

Abstract: A data output buffer is disclosed. Generation of a latch-up is prevented by forming a N-well guard ring to interrupt the movement of minority carriers injected from the drain of NMOS transistor to the N.sup.+ pickup region of PMOS transistor. Accordingly, reliability of the device is improved.