Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with a pillar emitter structure. The pillar structure raises the BJT emitter above the surface of a trenched base. Ions implanted into the base trench diffuses into an extrinsic base contact region. The pillar elevation structure increases travel distance between the trench and the emitter and protects against encroachment without increasing the total emitter area allocated to the BJT device. A spacer oxide adjacent to the pillar separates the pillar from the trench-region implanted with ions.

Abstract: A hierarchical word line driving structure uses a shared inverter circuit architecture which allows for lower power consumption and a pulsed control signal to ensure accurate memory retrieval. The shared inverter word line structure includes a row decoder, a first sub-word line driver, a second sub-word line driver, and an interconnect line. The first sub-word line driver includes an inverting circuit for inverting the signal propagating along the global word line, while the second sub-word line driver does not. The interconnect line is coupled between the first and second sub-word line drivers to communicate the inverted signal therebetween. A pulsed control signal is supplied to clamping transistors connected to unselected word lines to ensure they remain clamped to ground.

Abstract: An ATM switch with a switch queuing system which minimizes cell loss for bursty traffic, while avoiding delay for time-critical. The switch has a plurality of input ports and a plurality of output ports, a switch fabric transmitting cells from the input ports to the output ports, and a backpressure signal circuit connected between each output buffer of each output port and each input buffer of each input port. Each input port has an input buffer holding ATM cells when the cells arrive faster from the port's input channel than the input port can transmit. The input port transmits cells from its input buffer responsive to a plurality of priority levels. Each output port has an output buffer holding cells when the cells arrive faster from the input ports than the output port can transmit. The output port also transmits cells from its output buffer responsive to a plurality of priority levels.

Abstract: Resource allocation logic for a computer system including a plurality of processors which share access to, and control of, a plurality of resources, such as disk drive units or busses. The resource allocation logic coordinates the execution of requests received from the processors to avoid resource sharing inefficiencies and deadlock situations. The allocation logic maintains a "request" queue for each processor, seeking to satisfy all requests quickly and fairly. The queues contain an entry corresponding to each request received from its corresponding processor and an identification of resources that are required by the entry's corresponding request. The allocation logic also maintains a "resources available" status array of resources which are not currently in use by any processors, or are not reserved for future use by any processors.

Abstract: The invention concerns digitizing tablets in portable computers, wherein position of a stylus, located on the tablet, is computed. The invention corrects for various errors which creep into the computation, in order to produce a more accurate stylus position. The digitizing tablet has multiple sensors used to determine the stylus' position with respect to the digitizing tablet. Error signals are generated by measuring the sensors outputs when the stylus is not inducing a signal into the digitizing tablet. In one embodiment, these error signals are used to modify certain parameters used in calculating the stylus position.

Abstract: Switch architecture is provided for interfacing a high speed broad bandwidth communication network to a communication fabric having a bandwidth which is a fraction of the high speed broad bandwidth with the network and the fabric having different data packet formats. A multiplex/inverse multiplex unit is provided for converting data packets at the first carrier rate and in the first format to data packets in the second format, and a switch converter then converts the data packet headers in the second format into switch format headers for transmission of the data packets through ports of the communication fabric. A splitter receives the data packets from the switch converter and routes the data packets to one of a plurality of the fabric ports in accordance with the connection identifier in the switch format header, the data packets to one of a plurality of fabric ports being at a second carrier rate.

Abstract: The invention concerns a stylus for producing a high-voltage, sinusoidal signal for an electrostatic digitizing pad. The high voltage is obtained by applying a sine wave to one lead of the primary of a transformer, and applying the inverse of the sine wave to the other lead of the primary. The secondary of the transformer produces the high voltage, which is developed into a signal which is applied to the digitizing pad.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A fusible link and method for its fabrication. A polysilicon pad is formed on top of an insulating layer and covered with a second insulating layer. A trench is selectively etched into the second insulating layer exposing the top of the polysilicon pad. An fusible aluminum link is then formed over the second insulating layer and trench and conformal therewith. When a programming current is driven through the link, the aluminum melts and is absorbed by the polysilicon pad, thereby preventing the link's growback.

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled.

Abstract: The invention concerns apparatus for processing signals induced by a stylus applied to a digitizing tablet. The tablet produces four signals, A, B, C, and D, indicative of four currents, induced at four different points on the tablet, by the stylus. The four signals indicate the position of the stylus. The invention derives stylus position based solely on two difference pairs (A-D) and (B-C). Further, the computation of the difference-pairs suppresses common-mode noise, which otherwise interferes with computation of stylus position.

Abstract: A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.

Abstract: An architecture for distributing digital information to subscriber units wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface. The intermediate interface selects the desired service from a broadband network and transmits it to the subscriber unit over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit may access a wide variety of digital information available on the broadband network. Universal broadband access is thus provided at low cost. Output bandwidth of broadcast equipment may also be optimized.

Abstract: An amplifier circuit that maintains high speed and reduces power consumption while operating with reduced voltages is disclosed. Broadly, the amplifier circuit of the present invention includes a set-up circuit that performs a level shift on the input signal and applies it to the inputs of a sense amplifier in a cross-coupled fashion. The circuit operates such that one leg of the precharged sense amplifier output discharges in response to the input without a counteracting charging action by the other leg of the sense amplifier output. The amplifier circuit thus operates at higher speed and with no crowbar current even with input signals of smaller magnitude.

Abstract: A branch prediction technique which increases the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that many branches have run lengths that are constant or slowly-varying. I.e., several consecutive runs of 1's are of the same length. The technique uses the history stored for each branch, which history is enhanced by two small counters, an up counter and a down counter. These counters operate in conjunction with a state machine branch predictor of the prior art for very accurate predictions.

Abstract: A non-volatile memory access protocol that facilitates concurrent accessing operations to multiple non-volatile memory components. This approach provides significant speed advantages over prior art non-volatile protocols. Also, power consumption is reduced in comparison to prior art synchronous protocols used for volatile memory because each memory component need not be continuously selected.

Abstract: Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.

Abstract: A method of improving the boosted wordline compliance of a memory circuit. A wordline is grounded prior to boosting with a voltage greater than the circuit bias voltage (e.g. vdd) from a boost voltage generator. Grounding the wordline pulls the gate of a pass transistor to the bias voltage minus a threshold voltage and prepares the pass transistor to self-boost upon boosting the wordline. The transconductance of the pass transistor is improved, improving the charge transfer from the boost generator to the wordline, decreasing rise time. In another embodiment, an isolation transistor between the wordline select circuit and the pass transistor is boosted to provide additional pass transistor gate voltage.

Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: A digital video storage system, suitable for use within a movie-on-demand (MOD) system, includes a plurality of disk drive storage devices; the disk drives being connected together serially to form a loop, wherein each disk drive within the loop has an input for receiving digital video data for storage and an output for providing stored digital video data, the output of each disk drive being connected to the input of the succeeding disk drive in the loop. Successive segments of a video program, stored on successive disk drives in the loop, are each repeatedly moved at a predefined time interval from the disk drive on which the segments are currently stored to the succeeding disk drive in the loop. A plurality of taps are connected to the loop to provide connection points for MOD subscribers or viewers for receiving the video program from the loop. Each tap corresponds to the output of one of the plurality of disk drives.