Abstract: A metallic, stress-tunable thin film structure is applied to the backside of an epitaxial wafer to compensate for stress created by the frontside epitaxial layers. The structure may comprise multiple layers, including a metallic stress compensation layer (“SCL”), a metallic adhesive layer and/or a passivation (or solder attach) layer. In other embodiments, the stress compensation structure comprises only the metallic stress compensation layer. In a first application, the metallic stress compensation structure is applied to a backside of an epitaxial wafer prior to beginning device fabrication, correcting for bow present in as-purchased wafers. In a second application, the metallic stress compensation structure is applied to a backside of a thinned epitaxial wafer at the completion of frontside processing, preventing bow-induced wafer breakage upon removal from the rigid support structure or carrier disc.

Abstract: In an illustrative embodiment, a VCSEL comprises a substrate, a first DBR on a first major surface of the substrate, an active region on the first DBR, a second DBR on the active region, and electrically conductive vias that pass through the substrate and provide ohmic contact with the DBRs so that electrical connections to both DBRs are available on the substrate side of the VCSEL. The VCSEL is formed by forming a first DBR on a first major surface of a substrate, forming an active region on the first DBR, forming a second DBR on the active region, thinning the substrate, making a first via hole through the substrate to the first DBR, making a second via hole through the substrate and the first DBR, filling the first via hole with an electrically conducting material to contact the first DBR, filling the second via hole with an electrically conducting material, and coupling the second via hole to the second DBR.

Abstract: Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.