Patents Assigned to Infinera Corporation
  • Publication number: 20180375718
    Abstract: A network device may receive network configuration data indicating a topology of a plurality of network nodes in a network. Based on the received network configuration data, the network device may generate intra-layer and inter-layer upgrade dependency graphs. Based on the intra-layer upgrade dependency graph, the network device may determine an intra-layer upgrade depth for each of the plurality of network nodes. The network device may also determine, based on the inter-layer upgrade dependency graph, an inter-layer upgrade depth for each of the plurality of network nodes. The network device may then determine, based on the intra-layer and inter-layer upgrade depths, an upgrade schedule for the plurality of the network nodes. The upgrade schedule may indicate an order in which the plurality of network nodes is to be upgraded. Based on the upgrade schedule, the network device may transmit at least one instruction to upgrade the plurality of network nodes.
    Type: Application
    Filed: October 20, 2017
    Publication date: December 27, 2018
    Applicant: Infinera Corporation
    Inventors: Madhukar Anand, Ramesh Subrahmaniam
  • Publication number: 20180375730
    Abstract: A network device may receive first network configuration data that include pre-upgrade network information. The network device may then determine, based on the first network configuration data, at least one first network invariant. Based on the first network invariant, the network device may determine a first set of hash values indicating a pre-upgrade network state. The network device may receive second network configuration data that includes post-upgrade network information. The network device may then determine, based on the second network configuration data, at least one second network invariant. Based on the second network invariant, the network device may determine a second set of hash values indicating a post-upgrade network state. The network device may then compare the first set of hash values and the second set of hash values to verify an upgrade state of a network node associated with the at least one first and second network invariants.
    Type: Application
    Filed: October 24, 2017
    Publication date: December 27, 2018
    Applicant: Infinera Corporation
    Inventors: Madhukar Anand, Ramesh Subrahmaniam
  • Patent number: 10153861
    Abstract: A device may receive optical network information associated with a first optical node and a second optical node. The first optical node may be associated with a first group of optical devices. The second optical node may be associated with a second group of optical devices. The device may identify a first mapping in which a first group of optical channels is associated with the first group of optical devices and a second mapping in which a second group of optical channels is associated with the second group of optical devices. The first group of optical channels may correspond to the first group of payloads, and the second group of optical channels may correspond to the second group of payloads. The device may provide information depicting the first mapping and information depicting the second mapping.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 11, 2018
    Assignee: Infinera Corporation
    Inventors: Karthikeyan Mathruboodham Nagarajan, Ravindarreddy Ankireddy, Kasi Viswanadham Pydi, Yashpal Kumar, Musab Qamri
  • Patent number: 10148382
    Abstract: Methods and systems are disclosed including a system comprising a first node, having a first transceiver comprising a first receiver and a first transmitter, comprising a tunable laser, configured to transmit a first optical signal on a first channel and to transmit a second optical signal on a second channel if the first receiver does not detect a third optical signal; a second node having a second transceiver comprising a second receiver and a second transmitter configured to transmit the third optical signal on the first channel if the second receiver detects the second optical signal; and a filter having ports configured to a particular bandwidth and to suppress the first optical signal if the first optical signal is not within the particular bandwidth of the port, and to transmit the second optical signal to the second node if the second optical signal is within the particular bandwidth.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 4, 2018
    Assignee: Infinera Corporation
    Inventors: Magnus Olson, Einar In de Betou
  • Patent number: 10133141
    Abstract: Consistent with the present disclosure, both arms of an MZ interferometer are “double-folded” and are bent in at least two locations to define first and second acute inner angles. Accordingly, the arms of the MZ interferometer may have substantially the same length, and, further, the MZ interferometer has a more compact geometry. In one example, the arms parallel each other and have a serpentine shape, and, in a further embodiment, the arms parallel one another and have a Z-shape. Accordingly, since the temperature of a PIC upon which the MZ interferometer is provided does not vary significantly over such short distances, the temperatures of both arms is substantially the same.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 20, 2018
    Assignee: Infinera Corporation
    Inventors: Peter W. Evans, Scott Corzine, Mehrdad Ziari, Pavel V. Studenkov, Masaki Kato, Charles H. Joyner
  • Patent number: 10128892
    Abstract: Systems and methods of tuning SerDes links between transmitter SerDes channels and receiver SerDes channels are described. Generally, the SerDes links may be tuned using a generic SerDes tuner implementation and a tuning algorithm. The tuning algorithm may have a first tuner interface specific to the transmitter SerDes device and a second tuner interface specific to the receiver SerDes device. The tuning algorithm may define a sequence of operations from the first tuner interface and the second tuner interface that when executed result in calibration of the SerDes link.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 13, 2018
    Assignee: Infinera Corporation
    Inventor: John Moghaddas
  • Patent number: 10122149
    Abstract: Methods, systems, and apparatus, including a laser including a layer having first and second regions, the first region including a void; a mirror section provided on the layer, the mirror section including a waveguide core, at least part of the waveguide core is provided over at least a portion of the void; a first grating provided on the waveguide core; a first cladding layer provided between the layer and the waveguide core and supported by the second region of the layer; a second cladding layer provided on the waveguide core; and a heat source configured to change a temperature of at least one of the waveguide core and the grating, where an optical mode propagating in the waveguide core of the mirror section does not incur substantial loss due to interaction with portions of the mirror section above and below the waveguide core.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 6, 2018
    Assignee: Infinera Corporation
    Inventors: Peter W. Evans, Mingzhi Lu, Fred A. Kish, Jr., Vikrant Lal, Scott Corzine, John W. Osenbach, Jin Yan
  • Patent number: 10116318
    Abstract: A method and apparatus are disclosed for asynchronous clock generation in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a first logic gate, a second logic gate, a first memory element, a second memory element, and a digital-to-analog converter (DAC). The comparator may initiate an evaluation or precharge operation of comparator inputs. The first logic gate may generate, based on comparator outputs, a first output signal indicating validity of first logic gate output. The second logic gate may generate a second output signal indicating timing reference of bit conversion. The first memory element may generate a third output signal indicating a current state of a bit. The second memory element may generate a plurality of next state bits based on the second output signal and the comparator outputs. The second logic gate may generate the second output signal based on the first and third output signals.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Infinera Corporation
    Inventors: Shah Sharif, Fu-Tai An
  • Patent number: 10103869
    Abstract: Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 16, 2018
    Assignee: Infinera Corporation
    Inventors: Vinod Narippatta, Mohammed Asad Rizvi
  • Publication number: 20180294887
    Abstract: Methods, systems, and devices for implementing optical interface and multiplexing devices. An input optical signal is received over an input fiber by an optical interface device. A modulated optical signal and an unmodulated optical signal are demultiplexed from the input optical signal, the unmodulated optical signal is modulated based on a data signal to generate an output optical signal; and the output optical signal is transmitted over an output fiber. A modulated optical signal is received over a network connection from an optical network by an optical multiplexing device. An unmodulated optical signal is generated using a generator device; the unmodulated optical signal and a signal that includes the modulated optical signal are multiplexed using an optical multiplexer to generate an output signal; and the output signal is transmitted over an output fiber to the optical interface device.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Infinera Corporation
    Inventor: Jeffrey T. Rahn
  • Patent number: 10095611
    Abstract: Disclosures herein describe a record and replay regression and unit test automation framework for simulating any hardware on a virtual machine to achieve thorough, affordable and efficient software testing. According to the disclosures herein, the test automation framework includes a recording stage where input and output messages for all the interfaces for a process (e.g., an embedded system or any software system or process) running on the original hardware may be recorded along with metadata in a space-optimized and efficient manner. The testing framework also includes a replay stage using innovative thread synchronization approaches that leverage the metadata to simulate the environment for the recorded embedded process in isolation, which may be done on an inexpensive machine or hardware. Thus, the original custom hardware, which may be expensive and costly to run, is not needed for the replay phase of testing.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 9, 2018
    Assignee: Infinera Corporation
    Inventors: Jayaram Hanumanthappa, Ravi Shankar Pandey, Rajasekar Venkatesan, Anthony Jorgenson
  • Patent number: 10097909
    Abstract: A packet optical network may include a packet optical gateway node that is configured to advertise a segment label to other nodes in the network where the segment label is used by a source node in place of a conventional segment routing label when the source node generates the list of labels included in the header of a data packet while establishing a path through a network. The segment label differs from a conventional segment routing label in that the segment label indicates the L0/L1 device or path as opposed to the L2/L3 device indicated by a conventional segment routing label.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 9, 2018
    Assignee: Infinera Corporation
    Inventors: Madhukar Anand, Sanjoy Bardhan, Ramesh Subrahmaniam, Soumya Roy
  • Publication number: 20180285249
    Abstract: Disclosures herein describe a record and replay regression and unit test automation framework for simulating any hardware on a virtual machine to achieve thorough, affordable and efficient software testing. According to the disclosures herein, the test automation framework includes a recording stage where input and output messages for all the interfaces for a process (e.g., an embedded system or any software system or process) running on the original hardware may be recorded along with metadata in a space-optimized and efficient manner. The testing framework also includes a replay stage using innovative thread synchronization approaches that leverage the metadata to simulate the environment for the recorded embedded process in isolation, which may be done on an inexpensive machine or hardware. Thus, the original custom hardware, which may be expensive and costly to run, is not needed for the replay phase of testing.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: INFINERA CORPORATION
    Inventors: Jayaram HANUMANTHAPPA, Ravi Shankar Pandey, Rajasekar Venkatesan, Anthony Jorgenson
  • Patent number: 10091911
    Abstract: A device may have: a frame section having a cage with a first receiving portion and a second receiving portion, the second receiving portion receiving a module; a first plate having an end, the first plate being received by the first receiving portion; a heat pipe having a first end attached to the end of the first plate and having a second end; a second plate attached to the second end of the heat pipe; and a spring attached to the first plate to bias the first plate against the module, the first plate being capable of receiving heat dissipated by the module, the heat pipe being capable of receiving the heat received by the first plate and transferring the heat to the second plate, the second plate receiving the heat transferred by the heat pipe and dissipating the received heat.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: October 2, 2018
    Assignee: Infinera Corporation
    Inventor: Matthew J. Kelty
  • Patent number: 10082718
    Abstract: A method and an apparatus for non-blocking Mach-Zehnder Modulator (MZM) arm imbalance monitoring and control through tones are disclosed herein. An optical transmitter may include an MZM to supply a first portion of light to an in-phase arm and a second portion to a quadrature arm of the MZM. The optical transmitter may apply modulator arm adjustments and dither signals to the two portions. Then, the MZM may combine the two portions into an optical output signal. The optical transmitter may tap the optical output signal to provide a first portion of the optical output signal and transmit a second portion. Also, the optical transmitter may obtain first error signals, based on the first dither signal, and second error signals, based on the second dither signal, of the first portion of the output signal. The optical transmitter may change the modulator arm adjustments based on the error signals.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 25, 2018
    Assignee: Infinera Corporation
    Inventor: Rene Marcel Schmogrow
  • Patent number: 10084482
    Abstract: Various apparatus and methods may use iterative de-mapping/decoding to on received symbol estimates corresponding to interleaved coded modulation (ICM) using low-density parity check convolutional coding (LPDC-CC). The iterative de-mapping/decoding, may take the form of a multi-stage feed-forward arrangement that may include multiple identically designed stages, and the stages may use parallelism to increase speed and efficiency.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: September 25, 2018
    Assignee: Infinera Corporation
    Inventors: Abdullah Karar, Han Henry Sun, Kuang-Tsan Wu
  • Publication number: 20180269983
    Abstract: Constant modulus multi-dimensional modulation system and methods are disclosed herein, employing multi-intensity quadrature amplitude modulation (QAM) to generate a dual-polarization symbol. j bits may be mapped to one of a plurality of dual-polarization symbols having a same constant power modulus on a two-level constellation including first and second intensity rings in a four-dimensional (4D) space including in-phase (I), quadrature (Q), X polarization (Xpol) and Y polarization (Ypol). A first bit of the j bits may indicate that the symbol is on the first intensity ring for the Xpol and the second intensity ring for the Ypol, a next k bits may indicate a location of the symbol on the first intensity ring in the Xpol, and a remaining j?k?1 bits may indicate a location of the symbol on the second intensity ring in the Ypol. Maximum correlation decoding may be used to decode the first symbol at the receiver.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 20, 2018
    Applicant: Infinera Corporation
    Inventors: Abdullah S. Karar, Han Sun, Kuang-Tsan Wu
  • Patent number: 10080067
    Abstract: An apparatus, comprising a linecard including a circuit board having a front side connectable to a pluggable optical module and a back side opposite the front side; a heat relay apparatus comprising a heat pipe on the circuit board; a pluggable optical module generating a first amount of heat and being in thermal contact with the heat pipe; and a cooling module including a heat sink in thermal contact with the heat pipe, the cooling module generating a second amount of heat in a range from the first amount of heat to no heat; and wherein heat from the pluggable optical module is transferable through the heat pipe to the cooling module for dispersal from the heat sink.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 18, 2018
    Assignee: Infinera Corporation
    Inventor: Matthew James Kelty
  • Patent number: 10075259
    Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Infinera Corporation
    Inventors: Saurabh Pandey, Saratchandar Adayapalam Viswanathan, Vinay Khana
  • Patent number: 10070206
    Abstract: A method may include transmitting, by an optical device, a first set of channels using a first modulation format. The first set of channels may be attenuated during transmission by a filter associated with a wavelength selective switch. The method may further include transmitting, by the optical device, a second set of channels using a second modulation format. The second set of channels may be attenuated during transmission by the filter associated with the wavelength selective switch. The first set of channels and the second set of channels may be included in a super-channel. The first modulation format may be selected based on a first signal quality factor associated with attenuation by the filter associated with the wavelength selective switch. The second modulation format may be selected based on a second signal quality factor associated with attenuation by the filter associated with the wavelength selective switch.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 4, 2018
    Assignee: Infinera Corporation
    Inventor: Matthew L. Mitchell