Patents Assigned to Integrated Silicon Solutions, (Cayman) Inc.
  • Patent number: 11941299
    Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 26, 2024
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Benjamin Louie, Neal Berger, Lester Crudele
  • Patent number: 11925125
    Abstract: The disclosure provides a magnetic random access memory element. The magnetic random access memory element includes a magnetic reference layer, a magnetic free layer, and a non-magnetic barrier layer between the magnetic free layer and the magnetic reference layer. The magnetic random access memory element further includes a MgO layer contacting the magnetic free layer. The MgO layer includes multiple homogeneous layers of MgO that provide excellent interfacial perpendicular magnetic anisotropy to the magnetic free layer while also having a low RA.
    Type: Grant
    Filed: January 23, 2022
    Date of Patent: March 5, 2024
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Bartlomiej Adam Kardasz, Jorge Vasquez, Mustafa Pinarbasi, Georg Wolf
  • Patent number: 11836607
    Abstract: A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: December 5, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Michail Tzoufras
  • Patent number: 11751484
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Satoru Araki
  • Patent number: 11751481
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Satoru Araki
  • Patent number: 11723217
    Abstract: A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 8, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11714762
    Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: August 1, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Geun-Young Park, Seong-Jun Jang
  • Patent number: 11688649
    Abstract: A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: June 27, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Amitay Levi, Dafna Beery, Andrew J. Walker
  • Patent number: 11631807
    Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 18, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker
  • Patent number: 11626559
    Abstract: Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: April 11, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Thomas Boone, Pradeep Manandhar, Girish Jagtini, Yuan-Tung Chin, Elizabeth Dobisz, Mustafa Pinarbasi
  • Patent number: 11626149
    Abstract: A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 11, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: SungJin Han
  • Patent number: 11626407
    Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 11, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 11621027
    Abstract: A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source line current and/or bit line current to be applied to an individual column of memory elements in the array for quick retrieval of data in a Magnetic Random Access Memory (MRAM) system.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 4, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Adrian E. Ong
  • Patent number: 11621293
    Abstract: Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a third terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The third terminal can be coupled to the second device. The first terminal, the second terminal, and third terminal and couple components included in the multi terminal stack to components not included in the multi terminal stack.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: April 4, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Thomas Boone, Pradeep Manandhar, Girish Jagtini, Yuan-Tung Chin, Elizabeth Dobisz, Mustafa Pinarbasi
  • Patent number: 11600769
    Abstract: A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: March 7, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Andrew J. Walker, Dafna Beery
  • Patent number: 11586553
    Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 21, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Patent number: 11586906
    Abstract: A computing device receives first data on which to train an artificial neural network (ANN). Using magnetic random access memory (MRAM), the computing device trains the ANN by performing a first set of training iterations on the first data. Each of the first set of iterations includes writing values for a set of weights of the ANN to the MRAM using first write parameters corresponding to a first write error rate. After performing the first set of iterations, the computing device performs a second set of training iterations on the first data. Each of the second set of iterations includes writing values for the set of weights of the ANN to the MRAM using second write parameters corresponding to a second write error rate. The second write error rate is lower than the first write error rate. The computing device stores values for the trained ANN.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 21, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Michail Tzoufras, Marcin Gajek
  • Patent number: 11580014
    Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 14, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
  • Patent number: 11574194
    Abstract: A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which to train a neural network comprising at least one quantized layer and performs a set of training iterations to train weights for the neural network. Each training iteration of the set of training iterations includes stochastically writing values to the random access memory for a set of activations of the at least one quantized layer of the neural network using first write parameters corresponding to a first write error rate. The computing device stores trained values for the weights of the neural network. The trained neural network is configured to classify second data based on the stored values.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 7, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Michail Tzoufras
  • Patent number: 11568222
    Abstract: A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using first read parameters corresponding to a first error rate.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 31, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventor: Michail Tzoufras