Patents Assigned to Intel Corporation
  • Patent number: 11030459
    Abstract: Methods and apparatus for projecting augmented reality (AR) enhancements to real objects in response to user gestures detected in a real environment are disclosed. An example apparatus includes an object detector, a gesture detector, and an enhancement determiner. The object detector is to detect one or more real objects located in a real environment based on depth data obtained from a sensor array located within the real environment. The gesture detector is to detect a user gesture within the real environment based on motion data obtained from the sensor array, the user gesture being associated with a target real object from among the one or more real objects. The enhancement determiner is to determine an AR enhancement based on the user gesture and the target real object. The enhancement determiner is to instruct a projector to project the AR enhancement to the target real object.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventors: Ankur Agrawal, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Pete Denman
  • Patent number: 11029957
    Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Sahita, Deepak Gupta, Vedvyas Shanbhogue, David Hansen, Jason W. Brandt, Joseph Nuzman, Mingwei Zhang
  • Patent number: 11029955
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Patent number: 11030120
    Abstract: A processor includes a cryptographic engine to control access, using an secure region key identifier (ID), to one or more memory range of memory allocable for flexible conversion to secure pages of architecturally-protected memory regions, and a processor core. The processor core is to, responsive to receipt of a request to access the memory, perform a walk of page tables and extended page tables to translate a linear address of the request to a physical address of the memory. The processor core is further to determine that the physical address corresponds to an secure page within the one or more memory range of the memory, that a first key ID located within the physical address does not match the secure region key ID, and issue a page fault and deny access to the secure page in the memory.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Simon P. Johnson, Raghunandan Makaram, Francis X. McKeen, Carlos V. Rozas, Meltem Ozsoy, Ilya Alexandrovich, Siddhartha Chhabra
  • Patent number: 11029965
    Abstract: Systems, apparatuses and methods may provide for technology to determine one or more default values associated with a block storage device and automatically retrieve boot code from the block storage device in accordance with the default value(s), wherein the boot code is retrieved via an expansion bus. In an example, the default value(s) include bus number information and address information, wherein the address information corresponds to a bus header of the block storage device. Moreover, the block storage device may be dedicated to the bus controller and retrieval of the boot code from the block storage device may bypass a bus enumeration procedure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Pelner, James Pelner
  • Patent number: 11029958
    Abstract: Systems, methods, and apparatuses relating to configurable operand size operation circuitry in an operation configurable spatial accelerator are described.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Chuanjun Zhang, Kermin E. Chofleming
  • Patent number: 11029960
    Abstract: Apparatus and method for widened SIMD execution on a limited register file. For example, one embodiment of an apparatus comprises: instruction dispatch circuitry to dispatch instructions of a thread for execution, including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and execution circuitry including single instruction multiple data (SIMD) circuitry, the execution circuitry to execute the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry and to execute the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Marek Targowski, Konrad Trifunović
  • Patent number: 11032365
    Abstract: Technologies for establishing and utilizing a decentralized cloud infrastructure using a plurality of mobile computing devices include broadcasting for the formation of the decentralized cloud computing and storage infrastructure and establishing wireless communications between the plurality of mobile computing devices. The plurality of mobile computing devices self-organize and cooperate with one another to establish a structured decentralized cloud infrastructure to expose and sharing resources, services, and/or applications for ad hoc or socially-driven decentralized, cloud computing purposes.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: John B. Vicente, James R. Blakley, Hong Li, Mark D. Yarvis
  • Patent number: 11030012
    Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Divya Vijayaraghavan, Denica Larsen, Kooi Chi Ooi, Lady Nataly Pinilla Pico, Min Suet Lim
  • Patent number: 11030034
    Abstract: Systems and methods may be used to perform a software failure mode and effects analysis (SW FMEA) for a software component. The SW FMEA may include a quantitative approach, for example based on a risk priority number for the software component. The risk priority number may be based on a severity of a failure in the software component, an occurrence likelihood of a failure in the software component, or a detectability of a failure in the software component. A safety integrity level may be determined for the software component based on the risk priority number.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Rigels Gordani, Luca Fogli, Francesco Pingitore, Giovanni Satori
  • Patent number: 11032470
    Abstract: A mechanism is described for facilitating sensors arrangement and shifting for multisensory super-resolution cameras in imaging environments, according to one embodiment. A method of embodiments, as described herein, includes arranging sensors of a camera such that pixel centers of pixels of an image are spread evenly across a pixel area having pixel planes corresponding to the sensors, where the image is captured by the camera. The method may further include re-arranging the sensors by dividing the sensors in pairs of sensors, where each pair of sensors corresponds to a pair of pixel planes, and shifting the sensors diagonally such that the corresponding pixel planes are adjusted accordingly for improving quality of the image.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventor: Alex Burstein
  • Patent number: 11030712
    Abstract: Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski
  • Patent number: 11029971
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Meenakshi Arunachalam, Kushal Datta, Vikram Saletore, Vishal Verma, Deepthi Karkada, Vamsi Sripathi, Rahul Khanna, Mohan Kumar
  • Patent number: 11030126
    Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventors: David A. Koufaty, Rajesh M. Sankaran, Stephen R. Van Doren
  • Patent number: 11030000
    Abstract: Embodiments involving core-to-core offload are detailed herein. For example, a method comprising: monitoring performance of a first core using performance monitoring circuitry; determining a core-to-core offload availability status of the first core based at least in part on values store in the performance monitoring circuitry; and transmitting an availability indication to a second core of an availability of the first core to act as a helper core to perform one or more tasks on behalf of the second core based upon the determined offload availability status of the first core is described.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventor: Elmoustapha Ould-Ahmed-Vall
  • Patent number: 11030864
    Abstract: An example wearable device includes a haptic actuator to produce a haptic vibration in response to a target input waveform, a haptic effect sensor to measure a haptic vibration corresponding to the haptic vibration and to output a measured haptic vibration waveform and a feedback circuit to modify the target input waveform to reduce a difference between the haptic vibration and a measured haptic vibration waveform.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Ramune Nagisetty, Robert Flory, Giuseppe Raffa
  • Patent number: 11030231
    Abstract: An embodiment of a semiconductor package apparatus may include a substrate, and logic coupled to the substrate, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the substrate to determine an angular distance between a data object and a group of data objects, and assign the data object to the group of data objects based on the determined angular distance. In some embodiments, the logic may also be to determine one or more of an upper bound and a lower bound for the group of data objects based on triangle inequality. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Piotr Tylenda
  • Patent number: 11030711
    Abstract: Methods and systems may include logic to identify a plurality of blocks in image data having one or more top-left dependent pixels, and select the plurality of blocks in a wavefront order for processing. In addition, the logic may process a plurality of pixels in each block in the wavefront order. The system may also include a display device to output a result associated with processing the plurality of pixels.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Hao Yuan
  • Patent number: 11030017
    Abstract: Technologies for efficiently booting sleds in a disaggregated architecture include a sled. The sled includes a network interface controller, a set of processors, and firmware that includes an operating system. Additionally, the sled includes circuitry to perform, with multiple processors in the set of processors, a boot process. The circuitry is also to initialize the operating system present in the firmware, receive, with the network interface controller and from another sled, an assignment of a workload, and execute the assigned workload with the operating system.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 11030713
    Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Michael Apodaca, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu