Patents Assigned to Intel Corporation
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Publication number: 20240088134Abstract: An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Mauro J. Kobrinsky
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Publication number: 20240088887Abstract: An apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. First and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. Third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. First impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.Type: ApplicationFiled: November 23, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Dharmaray Nedalgi, Lavanya Manohar Nirikhi
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Publication number: 20240088217Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Tao Chu, Minwoo Jang, Chia-Ching Lin, Yanbin Luo, Ting-Hsiang Hung, Feng Zhang, Guowei Xu
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Publication number: 20240088131Abstract: An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Mauro J. Kobrinsky
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Publication number: 20240088265Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Tao Chu, Guowei Xu, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin
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Publication number: 20240088136Abstract: An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Ayan Kar, Nicholas A. Thomson, Kalyan C. Kolluru, Benjamin Orr
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Publication number: 20240088218Abstract: Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Shao-Ming Koh, Leonard P. Guler, Gurpreet Singh, Manish Chandhok, Matthew J. Prince
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Publication number: 20240088132Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Chu-Hsin Liang, Benjamin Orr, Biswajeet Guha, Brian Greene, Chung-Hsun Lin, Sabih U. Omar, Sameer Jayanta Joglekar
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Patent number: 11929212Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.Type: GrantFiled: April 23, 2019Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Sameer Paital, Gang Duan, Srinivas Pietambaram, Kristof Darmawikarta
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Patent number: 11928787Abstract: Systems, apparatuses and methods may provide for technology that estimates poses of a plurality of input images, reconstructs a proxy three-dimensional (3D) geometry based on the estimated poses and the plurality of input images, detects a user selection of a virtual viewpoint, encodes, via a first neural network, the plurality of input images with feature maps, warps the feature maps of the encoded plurality of input images based on the virtual viewpoint and the proxy 3D geometry, and blends, via a second neural network, the warped feature maps into a single image, wherein the first neural network is deep convolutional network and the second neural network is a recurrent convolutional network.Type: GrantFiled: September 22, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gernot Riegler, Vladlen Koltun
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Patent number: 11928860Abstract: Techniques related to object detection using an adaptive convolutional neural network (CNN) are discussed. Such techniques include applying one of multiple configurations of the CNN to input image data in response to an available computational resources for processing the input image data.Type: GrantFiled: December 14, 2018Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Konstantin Vladimirovich Rodyushkin, Alexander Vladimirovich Bovyrin
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Patent number: 11928215Abstract: An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.Type: GrantFiled: June 29, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Prashant Dewan, Chao Zhang, Nivedita Aggarwal, Aditya Katragada, Mohamed Haniffa, Kenji Chen
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Patent number: 11929320Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.Type: GrantFiled: March 30, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
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Patent number: 11927982Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.Type: GrantFiled: December 23, 2020Date of Patent: March 12, 2024Assignee: INTEL CORPORATIONInventors: Gururaj K. Shamanna, Naveen Kumar M, Harishankar Sahu, Abhishek Chouksey, Madhusudan Rao
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Patent number: 11928472Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 26, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilles Pokam, Jared Warner Stark, IV, Niranjan Kumar Soundararajan, Oleg Ladin
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Patent number: 11928753Abstract: Techniques related to automatically segmenting video frames into per pixel fidelity object of interest and background regions are discussed. Such techniques include applying tessellation to a video frame to generate feature frames corresponding to the video frame and applying a segmentation network implementing context aware skip connections to an input volume including the feature frames and a context feature volume corresponding to the video frame to generate a segmentation for the video frame.Type: GrantFiled: January 27, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Anthony Rhodes, Manan Goel
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Patent number: 11929295Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.Type: GrantFiled: February 22, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
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Patent number: 11929339Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.Type: GrantFiled: April 13, 2023Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
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Patent number: 11928042Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.Type: GrantFiled: March 24, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Dat T. Le, George Vergis
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Patent number: 11930479Abstract: Systems and methods for transmission of PDSCH and HARQ-ACK feedback in 5G networks are described. The TDRA of PDSCH repetitions are indicated in a DCI by a SLIV sequence configuration that contains multiple SLIV sequences. Each SLIV sequence for a slot is associated with an independent repetition factor and may also be associated with a partition factor to indicate a partition within the slot. One or more TRPs may be used to transmit each PDSCH repetition. The TCI states are mapped to the PDSCH repetitions in a round-robin fashion using an offset in terms of number of PDSCH repetitions from where TCI state switching starts and a number of consecutive PDSCH repetitions per TCI state. The HARQ-ACK bits in response to the PDSCH from the TRPs are concatenated in order of increasing control resource set higher layer signaling index.Type: GrantFiled: August 5, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Bishwarup Mondal, Gang Xiong, Alexei Davydov, Avik Sengupta, Sergey Panteleev, Debdeep Chatterjee