Patents Assigned to Intel Corporation
  • Patent number: 11030108
    Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou
  • Patent number: 11031288
    Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Ravindranath Mahajan, Stefan Rusu, Donald S. Gardner
  • Patent number: 11031005
    Abstract: A mechanism is described for facilitating continuous topic detection and adaption in audio environments, according to one embodiment. A method of embodiments, as described herein, includes detecting a term relating to a topic in an audio input received from one or more microphones of the computing device including a voice-enabled device; analyzing the term based on the topic to determine an action to be performed by the computing device; and triggering an event to facilitate the computing device to perform the action consistent with the term and the topic.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventors: Georg Stemmer, Andrzej Mialkowski, Joachim Hofer, Piotr Rozen, Tomasz Szmelczynski
  • Patent number: 11031305
    Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz Gardner, Seung Hoon Sung
  • Patent number: 11030113
    Abstract: An apparatus and method for efficient process-based compartmentalization.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: David M. Durham, Jacob Doweck, Michael Lemay, Deepak Gupta
  • Patent number: 11031482
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. Vacancies in the gate dielectric layer may be filled with capping layer material.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Patent number: 11030142
    Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Amit Kumar Srivastava, Nobuyuki Suzuki
  • Patent number: 11031359
    Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Tin Poay Chuah, Chin Lee Kuan
  • Patent number: 11030317
    Abstract: Embodiments described herein enable independently recoverable security for processor and peripheral communication, enabling a processor without native non-volatile memory to generate and recover credentials in response to a firmware update. The processor and peripheral can each have credentials burned into secure fuses. The processor can derive a shared secret from the secure fuses using security attributes that are based on the security version number of firmware within the processor and the peripherals to which the processor is to security communicate. The processor and peripherals can generate ephemeral session keys from the shared secret and nonces. The ephemeral session keys can be used to secure communications between the processor and the peripherals.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 8, 2021
    Assignee: INTEL CORPORATION
    Inventors: Xiaoyu Ruan, William A. Stevens, Jr., David Novick
  • Patent number: 11031666
    Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Sasha N. Oster, Georgios C. Dogiamis, Telesphor Kamgaing, Shawna M. Liff, Aleksandar Aleksov, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • Patent number: 11031072
    Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Brian S. Doyle, Prashant Majhi
  • Patent number: 11031503
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 11031918
    Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kaushik Dasgupta, Chuanzhao Yu, Chintan Thakkar, Saeid Daneshgar, Hyun Yoon, Xi Li, Anandaroop Chakrabarti, Stefan Shopov
  • Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 11031341
    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Md Altai Hossain, Kevin J Doran, Yu Amos Zhang, Zhiguo Qian
  • Patent number: 11031487
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Andrew W. Yeoh, Tahir Ghani, Atul Madhavan, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11031360
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Patent number: 11031545
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
  • Patent number: 11031387
    Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 11032357
    Abstract: Systems, apparatuses, and/or methods to provide data processing offload. An apparatus may determine whether a task is to be processed locally at a client device or remotely off the client device and issue the task to a wireless network and/or a wired network when the task is to be processed remotely off the client device at a server device. An apparatus may identify the task from the wireless network and/or the wired network when the task is to be processed locally at the server device, distribute the task to a server resource at the server device when the task is to be to processed locally at the service device, and provide a result of the task to the wireless network and/or the wired network when the result is to be consumed remotely at the client device.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Veeramani, Ujwal Paidipathi, Rajneesh Chowdhury, Prakash N. Iyer, Maciej Machnikowski, Chris Pavlas, Scott P. Dubal