Patents Assigned to Intel Corporation
  • Patent number: 11928443
    Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventor: Hong Shan Neoh
  • Patent number: 11930620
    Abstract: There is disclosed in one example a heat dissipator for an electronic apparatus, including: a planar vapor chamber having a substantially rectangular form factor, wherein a second dimension d2 of the rectangular form factor is at least approximately twice a first dimension d1 of the rectangular form factor; a first fan and second fan; and a first heat pipe and second heat pipe discrete from the planar vapor chamber and disposed along first and second d1 edges of the planar vapor chamber, further disposed to conduct heat from the first and second d1 edges to the first and second fan respectively.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Jeff Ku, Cora Nien, Gavin Sung, Tim Liu, Lance Lin, Wan Yu Liu, Gerry Juan, Jason Y. Jiang, Justin M. Huttula, Evan Piotr Kuklinski, Juha Tapani Paavola, Arnab Sen, Hari Shanker Thakur, Prakash Kurma Raju
  • Patent number: 11929888
    Abstract: Technologies for managing Function-as-a-Service function requests based on thermal and power awareness include an edge entity device having a circuitry to receive, from an edge device, a request to execute a function in an edge network environment having a plurality of edge entities. The circuitry is also to evaluate thermal and power criteria associated with the request and determine, as a function of a predicted thermal output over a specified time period relative to thermal and power criteria, whether to execute the function. In response to a determination by the circuitry to not execute the function, the circuitry is to select an edge entity of a plurality of edge entities that is able to satisfy the thermal and power criteria. The circuitry is further to forward the request to the selected edge entity.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 12, 2024
    Assignee: INTEL CORPORATION
    Inventor: Francesc Guim Bernat
  • Patent number: 11929927
    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Pratik M. Marolia, Rajesh M. Sankaran, Ashok Raj, Nrupal Jani, Parthasarathy Sarangam, Robert O. Sharp
  • Patent number: 11929396
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Patent number: 11930365
    Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Liuyang Yang, Xiruo Liu, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
  • Patent number: 11929330
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Patent number: 11929435
    Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
  • Patent number: 11928845
    Abstract: An apparatus to facilitate real-time playback of point cloud sequence data is disclosed. The apparatus comprises one or more processors to receive point cloud data of a captured scene, decompose the point cloud data into a plurality of point cloud patches, wherein each point cloud patch is associated with an object in the scene and includes contextual information regarding the point cloud patch, encode each of the point cloud patches via a deep-learning based algorithm to generate encoded point cloud patches, receive a viewpoint selection from a client, assign a priority to data chunks within each encoded point cloud patch based on the viewpoint selection and the contextual information and transmit the data chunks to the client based on the assigned priority.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Fai Yeung, Wayne Cochran, Pratibha Pandhare
  • Patent number: 11929816
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of beamforming. For example, a responder station may process a received Beam Refinement Protocol (BRP) request including a beam tracking request from an initiator station; and select whether or not to transmit a BRP response including beam tracking feedback, in response to the BRP request, based on a comparison between a time period and a BRP tracking time limit, the time period being based on a timing of the BRP request and a timing of the BRP response.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: March 12, 2024
    Assignee: INTEL CORPORATION
    Inventors: Solomon B. Trainin, Assaf Kasher, Carlos Cordeiro
  • Patent number: 11928059
    Abstract: A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Mahesh S. Natu, Vivekananthan Sanjeepan
  • Patent number: 11930465
    Abstract: An apparatus of a user equipment (UE) includes processing circuitry, where to configure the UE for New Radio (NR) communications above a 52.6 GHz carrier frequency, the processing circuitry is to decode higher layer signaling, the higher layer signaling including a default slot duration for a transmission of control signaling. The control signaling includes a synchronization signal (SS) and a physical broadcast channel (PBCH) signaling. Synchronization information within a SS block is decoded. The SS block is received within a SS burst set and occupying a plurality of symbols within a slot having the default slot duration. A synchronization procedure is performed with a next generation Node-B (gNB) based on the synchronization information within the SS block and the PBCH signaling.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gang Xiong, Avik Sengupta, Yushu Zhang, Jie Zhu, Dae Won Lee, Alexei Vladimirovich Davydov, Gregory Vladimirovich Morozov
  • Patent number: 11930159
    Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Jason Tanner, Zhijun Lei
  • Patent number: 11930528
    Abstract: This disclosure describes systems, methods, and devices related to uplink (UL) null data packet (NDP) format for passive location. A device may cause to send a trigger frame that solicits poll response to one or more anchor stations involved in a passive ranging measurement. The device may identify one or more polling response frames received from the one or more anchor stations. The device may cause to send a trigger frame that solicits uplink null data packet (NDP) to the one or more anchor stations, wherein the uplink NDP comprises an indication of a high efficiency (HE) single user (SU) frame type. The device may identify one or more uplink NDPs received from the one or more anchor stations.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Feng Jiang, Dibakar Das, Xiaogang Chen, Chittabrata Ghosh, Qinghua Li, Jonathan Segev, Robert Stacey, Ganesh Venkatesan
  • Patent number: 11930610
    Abstract: Personal computing device covers having stands are disclosed. A disclosed example apparatus includes a protective cover to at least partially cover a personal computing device. The cover includes a fixed panel to be thermally coupled to a chassis of the personal computing device to define a heatsink of the personal computing device, and a foldable panel to be rotatably coupled to the fixed panel via a hinge to support the personal computing device to stand at an angle from a surface.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Jeff Ku, Juha Paavola, Mark Carbone, Shantanu Kulkarni, Mikko Makinen, Gustavo Fricke
  • Publication number: 20240079337
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 7, 2024
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Tchefor Ndukum, Kristof Kuwawi Darmawikarta, Sheng Li, Srinivas V. Pietambaram, Gang Duan, Suddhasattwa Nad, Jeremy Ecton
  • Publication number: 20240078629
    Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 7, 2024
    Applicant: Intel Corporation
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Nicolas C. Galoppo Von Borries
  • Publication number: 20240079335
    Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Gang Duan, Suddhasattwa Nad
  • Publication number: 20240080276
    Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Applicant: Intel Corporation
    Inventors: Anurag AGRAWAL, John Andrew FINGERHUT, Xiaoyan DING, Song ZHANG