Patents Assigned to Intel Corporation
  • Patent number: 11032944
    Abstract: A heatsink includes a fin-set that includes a corrugated ribbon having a first, deformable, portion and a second, convective, portion that is not deformed. A plurality of corrugated ribbons may be physically and/or thermally coupled (e.g., via mechanical fasteners, thermally conductive bonding, or reflow) to form the heatsink. A force may be applied to the heatsink sufficient to at least partially crush the first, deformable, portion to conform to an external surface of an electronic device. The heatsink may be physically affixed and thermally coupled to an external surface of the electronic device via mechanical fasteners, thermally conductive adhesives or via reflow of a low-melt temperature layer disposed on an external surface of the heatsink. The crushed portion of the first, deformable, portion conforms to the regular (e.g., planar) or irregular surface profile of the electronic device, beneficially and surprisingly improving thermal performance of the heatsink.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Paul Gwin
  • Patent number: 11032417
    Abstract: Various systems and methods for a collaborative phone reputation system are described herein. A system for implementing a collaborative phone reputation system includes a compute device comprising: a call handling module to detect, at the compute device, an incoming call for a user of the compute device; a scoring module to determine a local probabilistic score that the incoming call is desirable for the user; and an execution module to perform an action at the compute device based on the local probabilistic score.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Igor Tatourian, Rita H Wouhaybi, Hong Li, Tobias Kohlenberg
  • Patent number: 11031967
    Abstract: The disclosure relates to a power control circuitry for controlling a radio frequency, RF, transmitter of a network equipment or a user equipment, the power control circuitry comprising: a controller configured to control a power level of an RF signal generated by the RF transmitter for transmission via an antenna arrangement, wherein the power level is controlled based on information about an object within an coverage area of the antenna arrangement.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Markus Dominik Mueck
  • Patent number: 11032219
    Abstract: Disclosed in some examples are methods, systems, and devices which perform automatic selection of an application-layer communication protocol based upon one or more communication characteristics of the sending application and one or more characteristics of the network connection between the sending device and the recipient. The selection of which protocol to use may be made on a message-by-message basis, periodically at various intervals (e.g., every predetermined time period), once upon application initialization, or the like. By dynamically selecting an application-layer communications protocol, an application may leverage the advantages of a specific protocol given the communication characteristics of the application and characteristics of the network connection at that time.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: John Brady, Wael Guibene, Keith Nolan, Michael Nolan, Mark Kelly
  • Patent number: 11032684
    Abstract: A communication system may include a plurality of geographically proximate nodes that communicate via one or more range-limited wireless technologies such as BLUETOOTH® low energy (BLE). An origin node may generate and communicate a first message responsive to detecting an event occurrence. The message may include an identifier associated with the origin node, data indicative of the event occurrence, a hop count, a maximum hop count, and a number of designated recipient nodes within the communication system. A first designated recipient node may, upon receiving the first message, attempt to confirm the event occurrence included in the first message. Upon confirming the event occurrence, the first designated recipient node may communicate a notification to an external third party. If unable to confirm the event occurrence, the first designated recipient node may generate and communicate a second message to a second designated recipient node included in the first message.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Cory J. Booth, Adam Jordan, Michael J. Payne, Alexandra C. Zafiroglu, Joshua Ekandem, Jasmeet Chhabra
  • Patent number: 11032305
    Abstract: Systems and methods may be used to prevent attacks on a malware detection system. A method may include modeling a time series of directed graphs using incoming binary files during training of a machine learning system and detecting, during a time-window of the time series, an anomaly based on a directed graph of the time series of directed graphs. The method may include providing an alert that the anomaly has corrupted the machine learning system. The method may include preventing or remedying corruption of the machine learning system.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Li Chen
  • Publication number: 20210165481
    Abstract: A system, article, and method of interactive storytelling generates probability-based personalized views factoring observable user behaviors.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Rita Brugarolas Brufau, David Israel Gonzalez Aguirre, Philip Krejov
  • Publication number: 20210165712
    Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Debarnab Mitra, Zion S. Kwok, Ravi H. Motwani
  • Publication number: 20210167023
    Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong
  • Publication number: 20210167014
    Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Kushal Sreedhar, Christopher Mozak, Mahmoud Elassal
  • Publication number: 20210168187
    Abstract: An apparatus may be configured to cause an audio source device to transmit an audio stream over a Bluetooth (BT) wireless communication link, the audio stream configured according to a first Advanced Audio Distribution Profile (A2DP) encoding/decoding (codec) scheme; to monitor a link-condition parameter corresponding to a link condition of the BT wireless communication link; and, based on the link-condition parameter, to reconfigure the audio stream according to a second A2DP codec scheme.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 3, 2021
    Applicant: INTEL CORPORATION
    Inventor: Srinivas Krovvidi
  • Publication number: 20210167180
    Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.
    Type: Application
    Filed: November 30, 2019
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Ayan Kar, Kalyan C. Kolluru, Nicholas A. Thomson, Mark Armstrong, Sameer Jayanta Joglekar, Rui Ma, Sayan Saha, Hyuk Ju Ryu, Akm A. Ahsan
  • Publication number: 20210167019
    Abstract: Provided herein are metal interconnects that may include a cobalt alloy, a nickel alloy, or nickel. Also provided herein are methods of making metal interconnects. The metal interconnects may include a barrier and/or adhesion layer, a seed layer, a fill material, a cap, or a combination thereof, and at least one of the barrier and/or adhesion layer, the seed layer, the fill material, or the cap may include a cobalt alloy, a nickel alloy, nickel, or a combination thereof.
    Type: Application
    Filed: September 1, 2017
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Daniel Zierath, Srijit Mukherjee, Jason Farmer, Chandan Ganpule, Julia Lin
  • Publication number: 20210165756
    Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.
    Type: Application
    Filed: January 20, 2021
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Anil Vasudevan, David Harriman
  • Publication number: 20210166114
    Abstract: Embodiments are generally directed to techniques for accelerating neural networks. Many embodiments include a hardware accelerator for a bi-directional multi-layered GRU and LC neural network. Some embodiments are particularly directed to a hardware accelerator that enables offloading of the entire LC+GRU network to the hardware accelerator. Various embodiments include a hardware accelerator with a plurality of matrix vector units to perform GRU steps in parallel with LC steps. For example, at least a portion of computation by a first matrix vector unit of a GRU step in a neural network may overlap at least a portion of computation by a second matrix vector unit of an output feature vector for the neural network. Several embodiments include overlapping computation associated with a layer of a neural network with data transfer associated with another of the neural network.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Gurpreet S Kalsi, Ramachandra Chakenalli Nanjegowda, Kamlesh R Pillai, Sreenivas Subramoney
  • Publication number: 20210168722
    Abstract: For example, an apparatus may be configured to maintain user device information to identify one or more user devices of a user of a computing device; to determine, when the computing device is at a low power mode of operation, that a detected user device of the one or more user devices is within a user detection range from the computing device based on a wireless signal from the user device; based on determination that the user device is within the user detection range from the computing device, to trigger a wireless proximity sensing to detect whether the user is within a wakeup range from the computing device; and based on detection that the user is within the wakeup range from the computing device, to trigger the computing device to wakeup from the low power mode.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 3, 2021
    Applicant: INTEL CORPORATION
    Inventor: Ehud Reshef
  • Publication number: 20210168578
    Abstract: For example, a BT audio device may be configured to, during a passphrase-detection mode, monitor an audio input of the BT audio device to detect whether the audio input includes a voice signal, the passphrase-detection mode configured for detection of a predefined user passphrase to indicate a voice command to be provided from a user of the BT audio device; based on a determination that the audio input does not include the voice signal, transmit one or more null-data packets to a BT device over a BT wireless communication link between the BT audio device and the BT device; and, based on a determination that the audio input includes the voice signal, transmit one or more data packets to the BT device over the BT wireless communication link, wherein a payload of the one or more data packets includes audio data based on the audio input.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 3, 2021
    Applicant: INTEL CORPORATION
    Inventor: Srinivas Krovvidi
  • Publication number: 20210167611
    Abstract: In some examples, a system includes a primary side with a charger and a first battery and a secondary side with a second battery. The charger on the primary side can charge both the first battery and the second battery. A hinge resistance is between the primary side and the secondary side. The primary side includes a feedback controlled active device in a current path of the first battery that compensates for the hinge resistance, for connector resistances, or for battery impedances in a current path of the second battery.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 3, 2021
    Applicant: Intel Corporation
    Inventors: Anil Baby, Anoop Parchuru, Shobhit Chahar, Govindaraj G., Vinaya Kumar Chandrasekhara
  • Publication number: 20210168010
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 3, 2021
    Applicant: INTEL CORPORATION
    Inventors: Artyom Lomayev, Alexander Maltsev, Claudio Da Silva, Carlos Cordeiro
  • Patent number: 11025913
    Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang