Patents Assigned to Intel Corporation
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Publication number: 20240080895Abstract: For example, an Access Point (AP) may be configured to configure a trigger frame to indicate an allocation of a triggered contention-based period to be allocated within a Transmit Opportunity (TxOP) of the AP. For example, the trigger frame may be configured to indicate that only one or more eligible non-AP stations (STAs), which are eligible to communicate during the triggered contention-based period, are to be allowed to contend a wireless medium during the triggered contention-based period. For example, the AP may be configured to transmit the trigger frame to initiate the allocation of the triggered contention-based period. For example, a non-AP STA may be configured to be allowed to contend the wireless medium for a transmission during the triggered contention-based period, for example, based on a determination that the non-AP STA is to be defined as an eligible non-AP STA for the triggered contention-based period.Type: ApplicationFiled: September 12, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Laurent Cariou, Thomas J. Kenney
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Publication number: 20240080076Abstract: Some demonstrative embodiments include devices, systems and/or methods of simultaneously communicating with a group of wireless communication devices. For example, a device may include a wireless communication unit to communicate with at least one group of a plurality of wireless communication devices over a wireless communication medium, wherein the wireless communication unit is to reserve the wireless communication medium for a time period, during which the wireless communication unit is to simultaneously transmit two or more different wireless communication transmissions to two or more wireless communication devices of the group, respectively. Other embodiments are described and claimed.Type: ApplicationFiled: September 13, 2023Publication date: March 7, 2024Applicant: INTEL CORPORATIONInventors: Michelle X. Gong, Robert J. Stacey
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Publication number: 20240078180Abstract: Described herein is a computer memory system comprising a plurality of memory banks or other memory structures and circuitry configured to implement a hash function that produces output values that evenly distribute strided memory accesses across the plurality of memory structures. The memory banks can be cache memory banks that may include a plurality of cache lines, cache sets, or cache ways. The memory banks can also be DRAM memory banks accessed through different memory channels. The hash function facilitates the even distribution across memory structures in the face of a plurality of different strided memory access patterns.Type: ApplicationFiled: November 15, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventor: William Zorn
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Publication number: 20240079334Abstract: A microelectronic structure, a semiconductor package including the structure, an IC device assembly including the structure, and a method of making the structure. The microelectronic structure includes: a first buildup layer and a second buildup layer including respective first and second electrically conductive structures; and a bridge layer including a glass material extending across a width thereof, the bridge layer between the first buildup layer and the second buildup layer and comprising: an interconnect bridge including third electrically conductive structures coupling a first set of the first electrically conductive structures to a second set of the first electrically conductive structures. Through glass vias (TGVs) extending from a top surface to a bottom surface of the bridge layer, the TGVs coupling a third set of the first electrically conductive structures to at least some of the second electrically conductive structures.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: Intel CorporationInventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Suddhasattwa Nad, Gang Duan
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Publication number: 20240080464Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.Type: ApplicationFiled: September 13, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventor: Jill Boyce
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Publication number: 20240079339Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: Intel CorporationInventors: Brandon C. Marin, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Benjamin T. Duong, Suddhasattwa Nad, Jeremy Ecton
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Publication number: 20240078453Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.Type: ApplicationFiled: September 14, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Ajit Singh, Bharat Daga, Michael Behar
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Publication number: 20240078630Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: ApplicationFiled: October 19, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Patent number: 11924060Abstract: Embodiments herein may include systems, apparatuses, methods, and computer-readable media, for a multi-access edge computing (MEC) system. A MEC orchestrator is to receive a request for service that includes a workload from a user agent; and facilitate formation of a SLA for servicing the workload. To facilitate the formation of the SLA includes to obtain, via a decentralized contracting system, bids from a plurality of service providers to respectively service a plurality of functions or tasks of the workload. The MEC orchestrator is also to translate the workload into the plurality of functions or tasks, and schedule servicing of the functions of tasks with the one or more service providers, including one or more edge computing devices, in accordance with the SLA. Other embodiments may be described and/or claimed.Type: GrantFiled: September 13, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Ned M. Smith, Sanjay Bakshi, Farid Adrangi, Francesc Guim Bernat
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Patent number: 11923371Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.Type: GrantFiled: September 29, 2017Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 11923809Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. An output passive network can further generate a flat-phase response between dual resonances of operation.Type: GrantFiled: August 22, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull
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Patent number: 11923150Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: GrantFiled: May 27, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventor: Changyok Park
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Patent number: 11921933Abstract: Computing devices, computer-readable storage media, and methods associated with human computer interaction. In embodiments, a computing device may include a display, a processor coupled with the display, a user interface engine and one or more applications to be operated on the processor. In embodiments, the user interface engine or the one or more applications may be configured to detect movement of the portable computing device indicating a direction a user of the portable computing device would like a portion of the user interface to move and cause the portion of the user interface to be moved, from a current location on the display to another location on the display, in accordance with the indicated direction. Such movement may facilitate the user to interact with the portion of the user interface via the interaction zone of the display. Other embodiments may be described and/or claimed.Type: GrantFiled: June 13, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Vinod Govindapillai, Tomer Rider
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Patent number: 11924435Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.Type: GrantFiled: May 15, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Srinivasan Embar Raghukrishnan, Jason Tanner, Naiqian Lu
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Patent number: 11924163Abstract: An apparatus used in a UE includes processing circuitry and memory. To configure the UE for a DNS resolution, the processing circuitry is to encode UL data for transmission to a first EAS via a first data path. The first data path includes a first UL CL UPF and a first PSA. A NAS SM message received from an SMF node is decoded. The NAS SM message includes an EAS rediscovery indication and a list of FQDNs associated with the first EAS. A DNS resolution procedure with a DNS server is performed in response to the EAS rediscovery indication, to obtain an IP address of a second EAS. The DNS resolution procedure is based on the list of FQDNs, and a second data path to the second EAS is established based on the IP address.Type: GrantFiled: April 6, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Changhong Shan, Danny Moses, Alexandre Saso Stojanovski
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Patent number: 11924653Abstract: This disclosure describes systems, methods, and devices related to high throughput (HT) control information. A device may determine a frame comprising HT control information. The device may determine to extend a size of the HT control information. The device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (HT) control information, define a new control identification (ID) associated with the extended HT control information, and cause to send the management or data frame to the first station device.Type: GrantFiled: December 24, 2020Date of Patent: March 5, 2024Assignee: INTEL CORPORATIONInventors: Po-Kai Huang, Daniel F. Bravo, Danny Alexander, Arik Klein, Danny Ben-Ari, Laurent Cariou, Robert Stacey
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Patent number: 11923312Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: GrantFiled: March 27, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
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Patent number: 11921558Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; a power controller to control power consumption of the plurality of cores, the power controller to receive network traffic metadata from a classifier and control the power consumption of at least one of the plurality of cores based at least in part on the network traffic metadata; and a hardware feedback circuit coupled to the plurality of cores, the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores based at least in part on the network traffic metadata. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Venkateshan Udhayan, Sravan Akepati, Ashraf H. Wadaa, Shahrnaz Azizi, Kristoffer Fleming, Ajay Gupta, Binu John
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Patent number: 11921564Abstract: In one embodiment, an apparatus includes: a port circuit to receive a configuration write from a source circuit; a save restore memory coupled to the port circuit to store information of a plurality of control and status registers (CSRs); and a configuration network coupled to the port circuit, the configuration network coupled to a plurality of nodes, each of the plurality of nodes comprising at least one CSR. The port circuit may be configured to send the configuration write to a first node of the plurality of nodes and to the save restore memory. Other embodiments are described and claimed.Type: GrantFiled: February 28, 2022Date of Patent: March 5, 2024Assignee: Intel CorporationInventor: Deepak Rameshkumar Tanna
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Patent number: 11921569Abstract: A technical problem faced when remotely controlling or debugging electronic devices is that remote control or debugging often requires a direct connection. However, debugging ports are inaccessible on many devices. Technical solutions described herein provide systems and methods for secure communication via existing communication infrastructure (e.g., public instant messenger (IM)), providing various debugging abilities including debugging and file sharing. Technical solutions described herein also provide systems and methods for debugging based on remote device memory state collection and sending for embedded or IoT devices. This solution avoids a hardware debugging connection by using a debugging methodology resident on the device to read and dump the relevant memory, registers, and other device state information in a secure and automated manner.Type: GrantFiled: September 8, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Tamir Damian Munafo, Yuli Barcohen, Dor Levy, Nachum Barcohen, Eli Elik Kupermann, Fred Bolay, Elad Dabool