Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: Systems, methods, and apparatuses relating to instructions to convert 16-bit floating-point formats are described. In one embodiment, a processor includes fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a source vector comprising N plurality of 16-bit half-precision floating-point elements, and a destination vector to store N plurality of 16-bit bfloat floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the source vector from 16-bit half-precision floating-point format to 16-bit bfloat floating-point format and store each converted element into a corresponding location of the destination vector, decode circuitry to decode the fetched single instruction into a decoded single instruction, and the execution circuitry to respond to the decoded single instruction as specified by the opcode.

Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.

Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Abstract: A system for generating a three-dimensional (3D) representation of a surface of an object. The system includes a point cloud processor and an object surface representation processor. The point cloud processor is to generate a structured point cloud of the object based on sensor data received from a sensor. The object surface representation processor is to: identify surface nodes in the structured point cloud; and link each surface node with any of its active neighbors to generate a surface net, wherein the linking comprises simultaneously establishing a forward-connectivity-link for a respective surface node to an active neighbor and a reverse-connectivity-link for the active neighbor to the respective surface node.

Abstract: Disclosed herein are systems and methods for controlling a telepresence robot, sometimes referred to as a receiver. The systems and methods may include obtaining environmental data associated with the receiver and/or an operator of the telepresence robot, sometimes referred to as a sender. A model defining a human intent may be received and an intent of a human proximate the receiver and or the sender may be determined using the model. A first signal may be transmitted to the receiver. The first signal may be operative to cause the receiver to alter a first behavior based on the intent of the human and/or the sender.

Abstract: Various approaches for the deployment and coordination of inter-satellite communication pathways, defined for use with a satellite non-terrestrial network, are discussed. Among other examples, such inter-satellite communication pathways may be identified, reserved, allocated, and used for ultra-low-latency communication purposes.

Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA.

Abstract: The present disclosure is directed to an inspection tool having an integrated optical laser unit and atomic force probe unit with a detector unit. The inspection tool further includes a processor unit that is coupled to the optical laser unit and the atomic force probe unit and performs a fault location analysis for a device under test. In addition, the present disclosure to methods for inspecting a device under test for defects using an inspection tool having an integrated optical laser unit and atomic force probe unit that includes a detector unit.

Abstract: A processor, a system, a machine readable medium, and a method.

Abstract: An apparatus is described. The apparatus includes a back plate, where, an electronic circuit board is to be placed between the back plate and a thermal cooling mass for a semiconductor chip package. The back plate includes a first material and a second material. The first material has greater stiffness than the second material. The back plate further includes at least one of: a third material having greater stiffness than the second material; re-enforcement wires composed of the first material; a plug composed of the second material that is inserted into a first cavity in the first material, a stud inserted into a second cavity in the plug. An improved bolster plate having inner support arms has also been described.

Abstract: A wireless computing device may include an internal antenna, a radio frequency (RF) transmission path that is switchably connectable to the internal antenna, a Universal Serial Bus (USB) connector configured to connect to an external antenna, a detector configured to detect if an external antenna is connected to the USB connector, and an antenna selector configured to (1) connect the internal antenna into the RF transmission path if the detector detects that no external antenna is connected to the USB connector and (2) disconnect the internal antenna from the RF transmission path and connect the external antenna into the RF transmission path if the detector detects that the external antenna is connected to the USB connector, thereby improving the wireless transmission/reception performance of the internal wireless module of the wireless computing device.

Abstract: In accordance with various embodiments herein, for single downlink control information (DCI) and/or multi-DCI multi-transmission-reception point (TRP) transmission, a default physical downlink shared channel (PDSCH) beam is determined based on the lowest indexed control resource set (CORESET) within the set of monitored CORESETs in the latest slot with the same value of CORESETPoolIndex. Other embodiments may be described and claimed.

Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.

Abstract: A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.

Abstract: Logic may monitor quality of communication of data to a wireless receiver device based on transport characteristics at a wireless source device. Logic may evaluate the transport characteristics to identify indication(s) of a problem with the quality of the communication. Logic may identify a root cause associated with the indication(s). Logic may associate the root cause with one or more actions to mitigate the degradation of the quality. And logic may cause performance of an operation to mitigate the degradation of the quality based on the one or more actions. The logic to evaluate the transport characteristics may determine an upper limit for an achievable mean opinion score (MOS) based on the transport characteristics; and, based on the upper limit for the achievable MOS being less than a threshold MOS, may identify the indication(s) associated with the upper limit for the achievable MOS.

Abstract: A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.