Abstract: A system and method that use the TCK and TMS to transmit address and data. IEEE 1149.1 based tools can use the system and method without modification to make IEEE 1149.1 TAPs appear and disappear, add compliance-enable circuits without pins and broadcast commands to IEEE P1687 instruments. The system and method use Test-Logic-Reset sequences with Run-Test-Idle to enable an on/off switch of various DFT capabilities. IEEE 1149.1 compliant TAP interfaces disappear to pass-through wires using the system and method. The sequences communicate an “address” which enables one or more of the TAP interfaces and a “command”. The system and method has benefits for IEEE P1687 instrument chains and on-chip routing of the P1687 network.

Abstract: A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local controllers over the communications path. The local controllers apply the stimulus data to the electronic circuits, receive resultant data generated by the circuits in response to the stimulus data, and locally verify the resultant data against the expected data substantially concurrently. When the communications path is implemented as an IEEE 1149.1 (JTAG) test bus, the primary controller can provide the expected and mask data to the local controllers over the TDO and TRSTN lines while the TAP controllers of the electronic circuits are in the Shift-IR or Shift-DR state to enable concurrent testing over a traditional five wire multi-drop IEEE 1149.

Abstract: An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

Abstract: A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.

Abstract: An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.

Abstract: An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

Abstract: A system and method of licensing electronic circuit designs within target electronic circuits or devices that allows secure delivery and reliable accounting of the licensed circuit designs on a per-usage basis. The method includes determining whether an electronic circuit design is licensable for use within a target electronic circuit by verifying licensing information included in a set of predetermined vectors associated with the electronic circuit design. In the event it is determined that the electronic circuit design is licensable for use within the target electronic circuit, the set of vectors is applied to the target electronic circuit by a licensing controller. Next, in response to a predetermined event, an attribute of the licensing information is updated to indicate the licensed use of the electronic circuit design within the target circuit.

Abstract: An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e.g., it may be programmed into a programmable logic device by the test resource apparatus.

Abstract: An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

Abstract: A Parallel Test Architecture (PTA) is provided that facilitates simultaneous access to multiple electronic circuits (i.e., in parallel) for optimized testing, debugging, or programmable configuration of the circuits. The PTA includes a Parallel Test Bus (PTB), a test controller connected to the PTB, and a plurality of addressable PTB controllers connected to the PTB, in which each addressable PTB controller is coupleable to a respective electronic circuit to be accessed. The test controller is configured to send at least one control signal over the PTB to respective addressable PTB controllers to initiate parallel scan access of the electronic circuits coupleable thereto by the respective addressable PTB controllers.

Abstract: The dental device includes a buccal member and a lingual member disposable on one side of a patient's mouth for isolating the buccal and lingual sides of the patient's mandibular teeth, respectively. The buccal member is generally curved to follow an outer contour of the patient's mandibular arch for deflecting the patient's cheek from the buccal side of the mandibular teeth. The lingual member is configured to corral a side of the patient's tongue and has a neck portion in a region where the lingual member attaches to the buccal member, the neck portion being configured to rest on the patient's mandibular teeth. The distal ends of the buccal and lingual members are spaced apart to permit independent movement therebetween. In one embodiment, the device includes a prop stem releasably attachable to the patient's maxillary teeth for propping open the patient's mouth.