Abstract: Embodiments provided herein describe methods and systems for forming high-k dielectric materials, as well as devices that utilize such materials. A property of a high-k dielectric material is selected. A value of the selected property of the high-k dielectric material is selected. A chemical composition of the high-k dielectric material is selected from a plurality of chemical compositions of the high-k dielectric material. The selected chemical composition of the high-k dielectric material includes an amount of nitridation associated with the selected value of the selected property of the high-k dielectric material. The high-k dielectric material is formed with the selected chemical composition.

Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract: Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.

Abstract: Provided are hybrid electrodes comprising base structures and plugs disposed within the base structures. Also provided are selector elements comprising such hybrid electrodes and memory arrays with selector elements used for addressing individual memory cells. Specifically, the base structure and plug of a hybrid electrode have different compositions but both interface the same dielectric of the selector element. This design allows anti-parallel diode and other configurations with a very few components. The base structure and plug may have different dopants, different stoichiometry of the same alloy, or formed from completely different materials. The interfacing surface portions of a hybrid electrode may have different sizes. A combination of these surface portions (e.g., areas, surface conditions) and materials (e.g., compositions) can be used for tuning operating characteristics of selector elements using such hybrid electrodes.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels. A first dielectric layer is disposed over a substrate and includes a bi-metal oxide having tin and bismuth or niobium. A seed layer is disposed directly on the first dielectric layer. A reflective layer including silver is disposed directly on the seed layer. A barrier layer is disposed above the reflective layer. The barrier layer includes one of a nickel chromium titanium aluminum alloy or a nickel chromium titanium aluminum oxide. The nickel chromium titanium aluminum alloy or the nickel chromium titanium aluminum oxide includes between about 5% and about 10% by weight nickel, between about 25% and about 30% by weight chromium, between about 30% and about 35% by weight titanium, and between about 30% and about 35% by weight aluminum.

Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a substrate and a reflective layer formed over the substrate. The low emissivity panels may further include a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the top dielectric layer and the substrate. The top dielectric layer may include a ternary metal oxide, such as zinc tin aluminum oxide. The top dielectric layer may also include aluminum. The concentration of aluminum may be between about 1 atomic % and 15 atomic % or between about 2 atomic % and 10 atomic %. An atomic ratio of zinc to tin in the top dielectric layer may be between about 0.67 and about 1.5 or between about 0.9 and about 1.1.

Abstract: Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. For example, by adding appropriate seed layers between the IR reflective layers and the base oxide layers, the color performance can be maintained regardless of high temperature processes. The optical filler layers can include a metal oxide layer. In some embodiments, the seed layer can include nickel, titanium, and niobium, forming a nickel titanium niobium alloy such as NiTiNb.

Abstract: Provided are resistive switching cells and methods of using such cells for controlling operation of liquid crystal display (LCD) cells in LCD devices. A resistive switching cell has two electrodes formed from transparent conductive oxides, such as indium oxide, indium tin oxide, or zinc oxide. One electrode may be connected to a LCD cell thereby forming an in series connection between the resistive switching cell and LCD cell. The other electrode may be used to power the LCD cell through the resistive switching cell. The resistive switching cell also includes a resistive switching layer disposed between the two electrodes. When the resistive switching layer is in its low resistive state, the LCD cell is subjected to an operating potential and produces light. However, when the resistive switching layer is in its high resistive state, the LCD cell is not subjected to the operating potential and does not produce light.

Abstract: Embodiments provided herein describe methods and chemical solutions for cleaning photomasks. A photomask is provided. The photomask is exposed to a chemical solution. The chemical solution includes a quaternary ammonium hydroxide. The quaternary ammonium hydroxide may include at least one of tetraethyl ammonium hydroxide (TEAH), tetrapropyl ammonium hydroxide (TPAH), or a combination thereof. The photomask may be an extreme ultraviolet (EUV) lithography photomask.

Abstract: A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

Abstract: Embodiments provided herein describe solid-state lithium batteries and methods for forming such batteries. A first current collector is provided. A first layer is formed above the first current collector. The first layer includes lithium and cobalt. The first layer is annealed. A second layer is formed above the annealed first layer. The second layer includes lithium and cobalt, and the annealed first layer and the second layer jointly form a first electrode. An electrolyte is formed above the first electrode. A second electrode is formed above the electrolyte. A second current collector is formed above the second electrode.

Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level.

Abstract: Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.

Abstract: A method for making low emissivity panels, including control the composition of a barrier layer formed on a thin conductive silver layer. The barrier structure can include an alloy of a first element having high oxygen affinity with a second element having low oxygen affinity. The first element can include Ta, Nb, Zr, Hf, Mn, Y, Si, and Ti, and the second element can include Ru, Ni, Co, Mo, and W, which can have low oxygen affinity property. The alloy barrier layer can reduce optical absorption in the visible range, can provide color-neutral product, and can improve adhesion to the silver layer.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.

Abstract: Embodiments of the invention generally relate to methods and compositions for forming conformal coatings on textured substrates. More specifically, embodiments of the invention generally relate to sol-gel processes and sol-gel compositions for forming low refractive index conformal coatings on textured transparent substrates. In one embodiment a method of forming a conformal coating on a textured glass substrate is provided. The method comprises coating the textured glass substrate with a sol-gel composition comprising a solidifier. It is believed that use of the solidifier expedites the sol-gel transition point of the sol-gel composition leading to more conformal deposition of coatings on textured substrates.

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.

Abstract: In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.