Patents Assigned to International Business Machines Corp.
  • Publication number: 20070168538
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
    Type: Application
    Filed: March 12, 2007
    Publication date: July 19, 2007
    Applicants: Sony Computer Entertainment Inc., International Business Machines Corp., Kabushiki Kaisha Toshiba
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki, Harm Hofstee, Martin Hopkins, Charles Johns, James Kahle, Shigehiro Asano, Atsushi Kunimatsu
  • Patent number: 7246348
    Abstract: A method for updating microcode of a printer includes the steps of embedding a microcode update file as a module in a print job file, inputting the print job file to the printer, recognizing that the print job file includes the microcode update file, and writing the microcode update file to a memory area in the printer indicated in the print job file. The microcode update file may include an executable program and after writing the microcode update file to memory execution may be transferred to the executable program.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 17, 2007
    Assignee: International Business Machines Corp.
    Inventor: J. Bruce Mixer, Jr.
  • Publication number: 20070162864
    Abstract: A method, system, and computer program product for providing user-directed repartitioning of content on tab-based interfaces that includes providing a tab-based interface, having a plurality of tabs, wherein each tab has an associated content view and allowing for the manipulating of one, or more, tab, so as to repartition the associated content view with the concomitant tab manipulation.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 12, 2007
    Applicant: International Business Machines Corp.
    Inventors: Eric Masselle, Anuphinh Phimmasorn
  • Patent number: 7227829
    Abstract: Described is a method for erasing data recorded in a data storage device in which a data bit is written onto a surface by applying a first combination of energy and force to the surface via a tip to form a pit in the surface representative of the data bit by local deformation of the surface. The method comprises applying a second combination of energy and force via the tip to prerecorded deformations of the surface to be erased to substantially level the surface.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corp
    Inventors: Gerd K. Binnig, Walter Haberle
  • Patent number: 7216284
    Abstract: A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: May 8, 2007
    Assignee: International Business Machines Corp.
    Inventors: Louis L. Hsu, Brian L. Ji, Li-Kong Wang
  • Patent number: 7199798
    Abstract: An object of the present invention is to provide a description method for efficiently representing contents of motion picture with a small data volume. The organization of the present invention (1) represents a trajectory of how each object has moved over time by using reference plane representing position information of each object, (2) sets a description unit based on a type of action of each object by using changes in shape of each object, (3) has actions of each object represented as each behavioral section, and (4) comprises a description facility capable of reading and interpreting definition of an object dependent on video contents, definition of classes of actions, and definition of interpretation of a scene by interaction of plural objects.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corp
    Inventors: Tomio Echigo, Masato Kurokawa, Junji Maeda, Alberto Tomita
  • Publication number: 20070073576
    Abstract: An integrated Resource Capacity Planning (RCP) process and tool program is presented. The RCP program includes identifying future labor needs and predicted labor supply. A gap analysis between the predicted future needs and supply is performed. Based on the gap analysis, resource actions are planned and taken to alleviate predicted future labor shortages. The predicted gap analysis is later compared with actual future needs/supply to evaluate the effectiveness of the parameters used in the RCP program. The RCP program is enterprise-independent, thus permitting re-use of data and parameters, and allowing the RCP program to be scalable.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: International Business Machines Corp.
    Inventors: Daniel Connors, John Deeb, John Fasano, Matthew Florian, Philip Garofolo, Donna Gresh, David Quinney, Ronald Zink
  • Patent number: 7194587
    Abstract: A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corp.
    Inventors: John David McCalpin, Balaram Sinharoy, Dereck Edward Williams, Kenneth Lee Wright
  • Patent number: 7194670
    Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate ā€œnā€ sets of CAD information which are then time-multiplexed to the embedded memory at a speed ā€œnā€ times faster than the BIST operating speed.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corp.
    Inventors: Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris, Paul C. Parries, Matthew R. Wordeman
  • Publication number: 20070061392
    Abstract: An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order part (H) and a low-order part (L) of an intermediate extended result according to H, L=A*B+C, where A, B are input operands and C an addend. Each H, L part is formatted the same as the format of the input operands, and alignment of the resulting fractions is not affected by alignment of the inputs. The apparatus includes an architecture for suppressing left-alignment of the intermediate extended result, such that input operands for a subsequent A*B+C operation remain right-aligned.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 15, 2007
    Applicant: International Business Machines Corp.
    Inventors: Guenter Gerwig, Eric Schwarz, Ronald Smith
  • Patent number: 7189431
    Abstract: A method for forming a passivated metal layer that preserves the properties and morphology of an underlying metal layer during subsequent exposure to oxygen-containing ambients. The method includes providing a substrate in a process chamber, exposing the substrate to a process gas containing a rhenium-carbonyl precursor to deposit a rhenium metal layer on the substrate in a chemical vapor deposition process, and forming a passivation layer on the rhenium metal layer to thereby inhibit oxygen-induced growth of rhenium-containing nodules on the rhenium metal surface.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 13, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corp.
    Inventors: Hideaki Yamasaki, Kazuhito Nakamura, Yumiko Kawano, Gert J. Leusink, Fenton R. McFeely, Paul Jamison
  • Patent number: 7174328
    Abstract: A method of utilizing one or more hints for query processing over a hierarchical tagged data structure having a plurality of nodes in a computing system having memory, the hint being positive if there is a tag accessible in top-down traversal from a child node, and otherwise negative. For each tag in the data structure, the method calculates a bitmap for a current node with all bits set to 1 and for each child node, followed by AND-ing all child bitmaps and setting a bit corresponding to a tag ID of a current tag to zero if such current tag exists. The method further sets a bit of a current tag to 0, calculates a plurality of possible non-redundant hints for each child node, and refreshes a hint list.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: February 6, 2007
    Assignee: International Business Machines Corp.
    Inventors: Ioana Stanoi, Christian Lang, Sriram Padmanabhan
  • Patent number: 7158604
    Abstract: A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: January 2, 2007
    Assignee: International Business Machines Corp.
    Inventors: Philip George Emma, Rajiv Vasant Joshi, William Robert Reohr
  • Patent number: 7150096
    Abstract: A method for applying pressure to circuit components during a manufacturing operation. The method utilizes a plurality of compressed air pressure cylinders which are supported on a plurality of horizontal arms along different axes over a circuit board. Compressed air is supplied simultaneously to each of the cylinders, and the cylinders force the component onto a bonding position on the circuit board. The method permits heat sinks to be pressed against components located on the circuit board to bond the heat sinks to the components.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: December 19, 2006
    Assignee: International Business Machines Corp.
    Inventors: James Westcott Heater, Allen Thomas Mays, John Gillette Davis
  • Patent number: 7146471
    Abstract: A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: December 5, 2006
    Assignees: International Business Machines Corp., Infineon Technologies AG
    Inventors: Toshiaki Kirihata, Gerhard Mueller, Wing K. Luk
  • Patent number: 7138326
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corp.
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Patent number: 7130963
    Abstract: A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corp.
    Inventors: Sameh W. Asaad, Jaime H. Moreno, Jude A. Rivers, John-David Wellman
  • Publication number: 20060231591
    Abstract: A solder feeding device having a reservoir, a drive unit, a first lead, and a second lead is provided. The reservoir melts solid solder wire into molten solder, while the drive unit selectively feeds the solid solder wire into the reservoir. The first and second leads are in electrical communication with the drive unit. The first lead is positioned in the reservoir so that it electrically communicates with the second lead through the molten solder when the molten solder reaches a triggering level, but so that it does not electrically communicate with the second lead when the level is below the triggering level. The drive unit feeds the solid solder wire into the reservoir based upon a state of electrical communication between the first and second leads.
    Type: Application
    Filed: June 28, 2006
    Publication date: October 19, 2006
    Applicant: International Business Machines Corp.
    Inventors: Peter Gruber, Lannie Bolde
  • Patent number: 7119578
    Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: October 10, 2006
    Assignee: International Business Machines Corp.
    Inventors: Anthony Correale, Jr., Rajiv V. Joshi, David S. Kung, Zhigang Pan, Ruchir Puri
  • Patent number: 7111266
    Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: September 19, 2006
    Assignee: International Business Machines Corp.
    Inventors: Anthony Correale, Jr., David S. Kung, Douglass T. Lamb, Zhigang Pan, Ruchir Puri, David Wallach