Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.

Abstract: In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.

Abstract: A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting the active electronic components, either directly or through one or more additional components, a desired circuit may be formed. In some examples, the desired circuit may be a monolithic microwave integrated circuit (MMIC). Methods of forming the circuit are also disclosed.

Abstract: A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the top of the substrate and are connected to further vias which extend to respective ball contacts at the substrate bottom. In one embodiment, the bottom surfaces and electrodes of the die are insulated and their tops (and drain electrodes) are connected by a moldable conductive layer. In another embodiment the top surface of the substrate is covered by an insulation cap, which may be finned for improved thermal properties. The passives are upended to have their longest dimension perpendicular to the substrate surface and are between the fin valleys.

Abstract: A power supply controller produces a compensation value based at least in part on: an estimated or known output capacitance of the power supply, a specified rate of changing a magnitude of the output voltage as specified by the voltage setting information, and/or a load-line resistance of the power supply. The power supply controller utilizes the compensation value to adjust a magnitude of the output voltage during a voltage transition in which the output voltage is changed from an initial output voltage setting to a target output voltage setting at a pre-specified rate.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors having a common drain coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors for various power applications. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench.

Abstract: An integrated circuit that includes a power stage and a driver stage, all stages using III-nitride power devices.

Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: According to example configurations herein, while operating a power supply in a discontinuous power supply mode, a controller initiates activation of a first switch of the power supply to increase a magnitude of current flowing through an inductor. The flow of current through the inductor produces an output voltage for powering a load. The controller estimates a time duration in which to activate a second switch of the power supply to reduce the current flowing through the inductor. The controller uses the estimated time duration as a parameter for controlling the second switch in the power supply. For example, upon or after deactivating the first switch, the controller initiates activation of the second switch for the estimated time duration. Deactivation of the second switch based on the estimated time duration reduces or eliminates a need to employ complex circuitry to physically measure a magnitude of current through the inductor.