Patents Assigned to International Rectifier Corporation
  • Patent number: 9099452
    Abstract: In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: August 4, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Dan Clavette
  • Patent number: 9087812
    Abstract: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 21, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9076852
    Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: July 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Jianjun Cao, Sadiki Jordan
  • Patent number: 9076779
    Abstract: The present disclosure includes novel techniques to provide wafer level fan-outs in electronic circuit packages housing one or more circuit devices, at least one of which has input and/or output nodes disposed on opposite facings.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: July 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Florian Bieck, Robert J. Montgomery
  • Patent number: 9070670
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 30, 2015
    Assignee: International Rectifier Corporation
    Inventor: Robert T. Carroll
  • Patent number: 9070755
    Abstract: According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 30, 2015
    Assignee: International Rectifier Corporation
    Inventors: Michael A. Briere, Reenu Garg
  • Patent number: 9064775
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 23, 2015
    Assignee: International Rectifier Corporation
    Inventors: T. Warren Weeks, Jr., Edwin Lanier Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 9054090
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: June 9, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9054119
    Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 9, 2015
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 9048196
    Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: June 2, 2015
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Robert J. Clarke
  • Patent number: 9048230
    Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 2, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
  • Patent number: 9041191
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9041187
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9041175
    Abstract: According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Dean Fernando, Tim Philips, Dan Clavette
  • Patent number: 9041011
    Abstract: In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventors: Ahmed Masood, Hongying Helen Ding, Dong Wang
  • Patent number: 9041067
    Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9035624
    Abstract: According to one configuration, a power supply circuit includes an inductor, a monitor circuit, a storage resource, and a processor circuit. The inductor resides in a phase of the power supply and conveys current to a load. The monitor circuit monitors and samples the voltage of a node in the power supply. The voltage of the node may be a sawtooth or ramp waveform sampled by the monitor circuit. A magnitude of the voltage at the node varies depending on an amount of current passing through the inductor to the load. The monitor circuit initiates storage of at least one sample in a storage resource. A processor circuit utilizes the multiple sample voltages stored in the storage resource to produce a value indicative of the amount of average current conveyed through the inductor to the load.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 19, 2015
    Assignee: International Rectifier Corporation
    Inventors: Amir M. Rahimi, Parviz Parto
  • Patent number: 9024420
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 9012990
    Abstract: According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 21, 2015
    Assignee: International Rectifier Corporation
    Inventors: Mark Pavier, Daniel Cutler, Scott Palmer, Clive O'Dell, Rupert Burbidge
  • Patent number: 9006824
    Abstract: In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: April 14, 2015
    Assignee: International Rectifier Corporation
    Inventor: Timothy D. Henson