Patents Assigned to International Rectifier Corporation
  • Patent number: 8878591
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 4, 2014
    Assignee: International Rectifier Corporation
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Patent number: 8871581
    Abstract: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: October 28, 2014
    Assignee: International Rectifier Corporation
    Inventor: Robert Beach
  • Patent number: 8872479
    Abstract: According to one embodiment, a system for actively managing energy banks during an energy transfer process comprises a plurality of energy banks configured for use as a group of energy banks and characterized by a desired state-of-charge (SOC), and a power management system coupled across each of the energy banks. The power management system is configured to selectively drive at least one of the energy banks to a modified SOC different from the desired SOC without interrupting the energy transfer process. In one embodiment, the power management system is further configured to return the energy bank or banks driven to the modified SOC to the desired SOC of the group of energy banks.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: October 28, 2014
    Assignee: International Rectifier Corporation
    Inventors: Emil Yuming Chao, Charles Chang
  • Patent number: 8865587
    Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Stuart Cardwell
  • Patent number: 8866458
    Abstract: An integrated start-up circuit for a power supply includes a converter, which in one implementation can be a buck converter. The buck converter includes a gate driver configured to drive a power switch, where the power switch is coupled across a DC bus node and a switching node of the buck converter. The power switch is configured to provide a start-up voltage to the buck converter from the DC bus node during start-up of the buck converter. The buck converter includes a bootstrap switch coupled across the gate driver and a Vcc node and a Schottky diode coupled across the bootstrap switch and the switching node, where the start-up voltage is provided at the Vcc node through the bootstrap switch.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Thomas J. Ribarich
  • Patent number: 8865575
    Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Michael A. Briere, Paul Bridger
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8859345
    Abstract: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8860198
    Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8860194
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Andrew N. Sawle, David Paul Jones, Timothy D. Henson, Niraj Ranjan, Vijay Viswanathan, Omar Hassen
  • Patent number: 8859400
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 8860085
    Abstract: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8853744
    Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Michael A. Briere
  • Patent number: 8853706
    Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8853707
    Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8847408
    Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: September 30, 2014
    Assignee: International Rectifier Corporation
    Inventors: Heny Lin, Jason Zhang, Alberto Guerra
  • Publication number: 20140264373
    Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: International Rectifier Corporation
    Inventor: Robert Beach
  • Patent number: 8836112
    Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 16, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8836145
    Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 16, 2014
    Assignee: International Rectifier Corporation
    Inventors: Sven Fuchs, Mark Pavier
  • Publication number: 20140252375
    Abstract: In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 11, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere