Abstract: According to one embodiment, a system configured to provide dynamic power management for a plurality of energy cells comprises an array of energy cells for providing a primary current path to a load, and a respective power stage for each energy cell. The power stages are configured to transfer power to and from each respective energy cell. The system further comprises a temporary energy storage node enabling energy transfer from a first plurality of energy cells comprised by the array of energy cells to a second plurality of energy cells comprised by the array of energy cells. In one embodiment, the system further comprises a feedback system for maintaining the temporary energy storage node at a constant average power.

Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.

Abstract: There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: In one implementation, a method of forming a P type III-nitride material includes forming a getter material over a III-nitride material, the III-nitride material having residual complexes formed from P type dopants and carrier gas impurities. The method further includes gettering at least some of the carrier gas impurities, from at least some of the residual complexes, into the getter material to form the P type III-nitride material. In some implementations, the carrier gas impurities include hydrogen and the getter material includes at least partially titanium. An overlying material can be formed on the getter material prior to gettering at least some of the carrier gas impurities.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.

Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.

Abstract: According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.

Abstract: According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode.

Abstract: According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules.

Abstract: According to one embodiment, a resonant gate driver comprises a resonant path configured to couple a gate of a power transistor to a supply capacitor, and a low impedance path configured to couple the gate of the power transistor to a voltage rail. The resonant gate driver selectively utilizes the resonant path during charging and discharging of the gate, and selectively utilizes the low impedance path to couple the gate to the voltage rail when the gate is neither charging nor discharging. A method for use by the resonant gate driver for driving the power transistor comprises charging and discharging the gate of the power transistor by selectively coupling the gate to a supply capacitor through a resonant path, and utilizing a low impedance path to selectively couple the gate to a voltage rail when the gate is neither charging nor discharging.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control circuit, and the driver circuit are each situated on a PQFN leadframe of the PQFN package. The control circuit and the driver circuit can be in a common integrated circuit (IC). Furthermore, the control circuit can be configured to reconstruct at least two phase currents of the multi-phase power inverter from a combined phase current.

Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe and respectively connected to a U-phase output strip and a W-phase output pad of the PQFN leadframe. The PQFN leadframe further includes a common integrated circuit (IC) including a driver circuit and a control circuit where the common IC is connected to the U-phase output strip and to the W-phase output pad of the PQFN leadframe. The PQFN leadframe can also include a V-phase power switch situated on the PQFN leadframe where the V-phase power switch is connected to a V-phase output strip of the PQFN leadframe.

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.

Abstract: In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.